Freescale Semiconductor MC9S12XDP512 5.3.1 Module Memory Map

Chapter 5 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 275
5.3.1 Module Memory Map
Table 5-1 gives an overview on all MC9S12XDP512 registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Table 5-1. MC9S12XDP512 Memory Map
Address
Offset Use Access
0x_00 CRG Synthesizer Register (SYNR) R/W
0x_01 CRG Reference Divider Register (REFDV) R/W
0x_02 CRG Test Flags Register (CTFLG)1
1CTFLG is intended for factory test purposes only.
R/W
0x_03 CRG Flags Register (CRGFLG) R/W
0x_04 CRG Interrupt Enable Register (CRGINT) R/W
0x_05 CRG Clock Select Register (CLKSEL) R/W
0x_06 CRG PLL Control Register (PLLCTL) R/W
0x_07 CRG RTI Control Register (RTICTL) R/W
0x_08 CRG COP Control Register (COPCTL) R/W
0x_09 CRG Force and Bypass Test Register (FORBYP)2
2FORBYP is intended for factory test purposes only.
R/W
0x_0A CRG Test Control Register (CTCTL)3
3CTCTL is intended for factory test purposes only.
R/W
0x_0B CRG COP Arm/Timer Reset (ARMCOP) R/W