Freescale Semiconductor MC9S12XDP512 5.6.2 PLL Lock Interrupt, 5.6.3 Self Clock Mode Interrupt

Chapter 5 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 309
5.6.2 PLL Lock Interrupt
The MC9S12XDP512 generates a PLL Lock interrupt when the LOCK condition of the PLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
5.6.3 Self Clock Mode Interrupt
The MC9S12XDP512 generates a self clock mode interrupt when the SCM condition of the system has
changed, either entered or exited self clock mode. SCM conditions can only change if the self clock mode
enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on
reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor
failure. For details on the clock quality check refer to Section 5.4.1.4, “Clock Quality Checker”. If the
clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set
to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.