Freescale Semiconductor MC9S12XDP512 SUB Subtract without Carry SUB

Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 471
Operation
RS1 – RS2 ⇒RDRD −IMM16 ⇒RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM[15:8])
Subtracts two 16-bit values and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
SUB Subtract without Carry SUB
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Source Form Address
Mode Machine Code Cycles
SUB RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 0 0 P
SUB RD, #IMM16 IMM8 1 1 0 0 0 RD IMM16[7:0] P
IMM8 1 1 0 0 1 RD IMM16[15:8] P