Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.11
958 Freescale Semiconductor
Table A-28. Example 1b: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 1)
No. C Characteristic Symbol
2 Stretch
Cycles
3 Stretch
Cycles Unit
Min Max Min Max
— — Frequency of internal bus fiD.C. 40.0 D.C. 40.0 MHz
— — Internal cycle time tcyc 25 ∞25 ∞ns
— — Frequency of external bus foD.C. 13.3 D.C. 10.0 MHz
— — External cycle time (selected by EXSTR) tcyce 75 ∞100 ∞ns
1 — External cycle time (EXSTR+1EWAIT) tcycew 100 ∞125 ∞ns
2D
Address1 valid to RE fall
1Includes the following signals: ADDRx, UDS, LDS, and CSx.
tADRE 5—5—ns
3D
Pulse width, RE 2
2Affected by EWAIT.
PWRE 85 — 110 — ns
4D
Address1 valid to WE fall tADWE 5—5—ns
5D
Pulse width, WE2PWWE 73 — 98 — ns
6
D Read data setup time (if ITHRS = 0) tDSR 24 — 24 — ns
D Read data setup time (if ITHRS = 1) tDSR 28 — 28 — ns
7 D Read data hold time tDHR 0—0—ns
8 D Read enable access time tACCR 71 — 86 — ns
9 D Write data valid to WE fall tWDWE 7—7—ns
10 D Write data setup time tDSW 81 — 106 — ns
11 D Write data hold time tDHW 8—8—ns
12 D Address to EWAIT fall tADWF 0 20 0 45 ns
13 D Address to EWAIT rise tADWR 37 47 62 72 ns