Freescale Semiconductor MC9S12XDP512 19.4.8 Hardware Handshake Abort Procedure

Chapter 19 Background Debug Module (S12XBDMV2)

MC9S12XDP512 Data Sheet, Rev. 2.11

784 Freescale Semiconductor

Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK

handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware

handshake protocol in Figure 19-11 speciﬁes the timing when the BKGD pin is being driven, so the host

should follow this timing constraint in order to avoid the risk of an electrical conﬂict in the BKGD pin.

NOTE

The only place the BKGD pin can have an electrical conﬂict is when one

side is driving low and the other side is issuing a speedup pulse (high). Other

“highs” are pulled rather than driven. However, at low rates the time of the

speedup pulse can become lengthy and so the potential conﬂict time

becomes longer as well.

The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not

acknowledge by an ACK pulse, the host needs to abort the pending command ﬁrst in order to be able to

issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command

(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.

Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be

issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any

possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol

provides a mechanism in which a command, and its corresponding ACK, can be aborted.

NOTE

The ACK pulse does not provide a time out. This means for the GO_UNTIL

command that it can not be distinguished if a stop or wait has been executed

(command discarded and ACK not issued) or if the “UNTIL” condition

(BDM active) is just not reached yet. Hence in any case where the ACK

pulse of a command is not issued the possible pending command should be

aborted before issuing a new command. See the handshake abort procedure

described in Section 19.4.8, “Hardware Handshake Abort Procedure”.

19.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. In order to abort a command, which had not issued

the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving

it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a

speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,

see Section 19.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command

and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been

completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it

can not be guaranteed that the pending command is aborted when issuing a SYNC before the

corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins

until it is ﬁnished and the corresponding ACK pulse is issued. The latency time depends on the ﬁrmware

READ or WRITE command that is issued and if the serial interface is running on a different clock rate

than the bus. When the SYNC command starts during this latency time the READ or WRITE command

will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or

Contents

Main Page Page Revision History Page Page Contents Chapter 1 Device Overview (MC9S12XDP512V2) Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2) Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) Chapter 4 Port Integration Module (S12XDP512PIMV2) Chapter 5 Clocks and Reset Generator (S12CRGV6) Chapter 6 Pierce Oscillator (S12XOSCLCPV1) Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) Chapter 9 XGATE (S12XGATEV2) Chapter 10 Security (S12X9SECV2) Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description Chapter 14 Freescales Scalable Controller Area Network (S12MSCANV3) Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) Chapter 16 Serial Peripheral Interface (S12SPIV4) Chapter 17 Voltage Regulator (S12VREG3V3V5) Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) Chapter 19 Background Debug Module (S12XBDMV2) Chapter 20 Debug (S12XDBGV2) Chapter 21 Interrupt (S12MC9S12XDP512V1) Chapter 22 External Bus Interface (S12XEBIV2) Chapter 23 Memory Mapping Control (S12XMMCV2) Appendix A Electrical Characteristics Appendix B Package Information Page Page Chapter 1 Device Overview (MC9S12XDP512V2) 1.1 Introduction 1.1.1 Features Page 1.1.2 Modes of Operation 1.1.3 Block Diagram Chapter 1 Device Overview (MC9S12XDP512V2) Figure 1-1. MC9S12XD-Family Block Diagram 1.1.4 Device Memory Map Table 1-1shows the device register memory map of the MC9S12XDP512. Table 1-1. Device Register Memory Map Table 1-1. Device Register Memory Map (continued) 1.1.5 Address Mapping 1.1.5.1 Local-to-Global Address Mapping Figure 1-2. Local-to-Global Address Mapping S12X_CPU/S12X_BDM Figure 1-3. Local-to-Global Address Mapping XGATE 1.1.5.2 Logical Address Map Figure 1-4. Memory Map 1.1.6 Detailed Register Map 0x000A0x000B Module Mapping Control (S12XMMC) Map 1 of 4 0x000C0x000D Port Integration Module (PIM) Map 2 of 5 0x000E0x000F External Bus Interface (S12XEBI) Map 0x00100x0017 Module Mapping Control (S12XMMC) Map 2 of 4 0x00180x001B Miscellaneous Peripheral 0x001C0x001F Port Integration Module (PIM) Map 3 of 5 0x001E IRQCR 0x001F Reser ved 0x00200x0027 Debug Module (S12XDBG) Map 0x00300x0031 Module Mapping Control (S12XMMC) Map 3 of 4 0x00320x0033 Port Integration Module (PIM) Map 4 of 5 0x00340x003F Clock and Reset Generator (CRG) Map 0x00400x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) 0x00400x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3) 0x00400x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3) 0x00800x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 0x00800x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 2 of 0x00B00x00B7 Inter IC Bus (IIC1) Map 0x00B80x00BF Asynchronous Serial Interface (SCI2) Map 0x00800x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 3 of 0x00C00x00C7 Asynchronous Serial Interface (SCI3) Map 0x00B80x00BF Asynchronous Serial Interface (SCI2) Map (continued) 0x00C80x00CF Asynchronous Serial Interface (SCI0) Map 0x00D00x00D7 Asynchronous Serial Interface (SCI1) Map 0x00D80x00DF Serial Peripheral Interface (SPI0) Map 0x00E00x00E7 Inter IC Bus (IIC0) Map 0x00D00x00D7 Asynchronous Serial Interface (SCI1) Map (continued) 0x00E80x00EF Reserved 0x00F00x00F7 Serial Peripheral Interface (SPI1) Map 0x00E00x00E7 Inter IC Bus (IIC0) Map (continued) 0x00F80x00FF Serial Peripheral Interface (SPI2) Map 0x01000x010F Flash Control Register (FTX512K4) Map 0x01100x011B EEPROM Control Register (EETX4K) Map 0x01000x010F Flash Control Register (FTX512K4) Map (continued) 0x011C0x011F Memory Map Control (S12XMMC) Map 4 of 4 0x01200x012F Interrupt Module (S12XINT) Map 0x001300x0137 Asynchronous Serial Interface (SCI4) Map 0x01380x013F Asynchronous Serial Interface (SCI5) Map 0x01400x017F Freescale Scalable CAN MSCAN (CAN0) Map 0x01380x013F Asynchronous Serial Interface (SCI5) Map (continued) Detailed MSCAN Foreground Receive and Transmit Buffer Layout 0x01400x017F Freescale Scalable CAN MSCAN (CAN0) Map (continued) 0x01800x01BF Freescale Scalable CAN MSCAN (CAN1) Map (Sheet 1 of 3) Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) 0x01800x01BF Freescale Scalable CAN MSCAN (CAN1) Map (Sheet 2 of 3) 0x01C00x01FF Freescale Scalable CAN MSCAN (CAN2) Map 0x01800x01BF Freescale Scalable CAN MSCAN (CAN1) Map (Sheet 3 of 3) 0x01C00x01FF Freescale Scalable CAN MSCAN (CAN2) Map (continued) 0x02000x023F Freescale Scalable CAN MSCAN (CAN3) 0x02400x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 1 of 4) 0x02000x023F Freescale Scalable CAN MSCAN (CAN3) (continued) 0x02400x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 2 of 4) 0x02400x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 3 of 4) 0x02800x02BF Freescale Scalable CAN MSCAN (CAN4) Map 0x02400x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 4 of 4) 0x02800x02BF Freescale Scalable CAN MSCAN (CAN4) Map (continued) 0x02C00x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map 0x02E00x02EF Reserved 0x02F00x02F7 Voltage Regulator (VREG_3V3) Map 0x02C00x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map (continued) 0x02F80x02FF Reserved 0x03000x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map 0x03280x033F Reserved 0x03400x0367 Periodic Interrupt Timer (PIT) Map 0x03680x037F Reserved 0x03800x03BF XGATE Map (Sheet 1 of 3) 0x03400x0367 Periodic Interrupt Timer (PIT) Map (continued) 0x03800x03BF XGATE Map (Sheet 2 of 3) 0x03C00x07FF Reserved 0x03800x03BF XGATE Map (Sheet 3 of 3) 1.1.7 Part ID Assignments 1.2 Signal Description 1.2.1 Device Pinout Chapter 1 Device Overview (MC9S12XDP512V2) 144-Pin LQFP Figure 1-5. MC9S12XD-Family Pin Assignment 144-Pin LQFP Package 72 Freescale Semiconductor 112-Pin LQFP Figure 1-6. MC9S12XD-Family Pin Assignments 112-Pin LQFP Package Freescale Semiconductor 73 Pins shown in BOLD are not available on the 80-Pin QFP package option 80-Pin QFP Figure 1-7. MC9S12XD-Family Pin Assignments 80-Pin QFP Package 1.2.2 Signal Properties Summary Table 1-3 summarizes the pin functionality. Table 1-3. Signal Properties Summary (Sheet 1 of 4) Table 1-3. Signal Properties Summary (Sheet 2 of 4) Table 1-3. Signal Properties Summary (Sheet 3 of 4) 1.2.3 Detailed Signal Descriptions 1.2.3.1 EXTAL, XTAL Oscillator Pins 1.2.3.2 RESET External Reset Pin 1.2.3.3 TEST Test Pin 1.2.3.4 VREGEN Voltage Regulator Enable Pin 1.2.3.5 XFC PLL Loop Filter Pin 1.2.3.6 BKGD / MODC Background Debug and Mode Pin 1.2.3.7 PAD[23:8] / AN[23:8] Port AD Input Pins of ATD1 1.2.3.8 PAD[7:0] / AN[7:0] Port AD Input Pins of ATD0 1.2.3.9 PA[7:0] / ADDR[15:8] / IVD[15:8] Port A I/O Pins 1.2.3.11 PB0 / ADDR0 / UDS / IVD[0] Port B I/O Pin 0 1.2.3.12 PC[7:0] / DATA [15:8] Port C I/O Pins 1.2.3.13 PD[7:0] / DATA [7:0] Port D I/O Pins 1.2.3.14 PE7 / ECLKX2 / XCLKS Port E I/O Pin 7 Figure 1-9. Loop Controlled Pierce Oscillator Connections (PE7 = 1) 1.2.3.15 PE6 / MODB / TAGHI Port E I/O Pin 6 Page Page Page Page Page Page 1.2.4 Power Supply Pins 1.2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins 1.2.4.4 V 1.2.4.5 VRH, VRL ATD Reference Voltage Input Pins 1.2.4.6 VDDPLL, VSSPLL Power Supply Pins for PLL 1.2.4.7 VREGEN On--Chip Voltage Regulator Enable Table 1-4. MC9S12XDP512 Power and Ground Connection Summary 1.3 System Clock Description 1.4 Chip Conguration Summary Table 1-5. Chip Modes and Data Sources Table 1-6. Clock Selection Based on PE7 Table 1-7. Voltage Regulator VREGEN 1.5 Modes of Operation 1.5.1 User Modes 1.5.2 Low-Power Modes 1.5.2.1 System Stop Modes 1.5.2.2 Pseudo Stop Mode 1.6 Resets and Interrupts 1.6.1 Vectors Table 1-8. Interrupt Vector Locations (Sheet 1 of 3) Table 1-8. Interrupt Vector Locations (Sheet 2 of 3) 1.6.2 Effects of Reset The RAM array is not initialized out of reset. 1.6.2.1 I/O Pins Refer to the PIM Block Guide for reset congurations of all peripheral module ports. 1.6.2.2 Memory 1.7 COP Conguration 1.8 ATD0 External Trigger Input Connection 1.9 ATD1 External Trigger Input Connection Chapter 2 512 Kbyte Flash Module (S12XFTX512K4V2) 2.1 Introduction 2.1.1 Glossary 2.1.2 Features Page 2.2 External Signal Description FTX512K4 2.3 Memory Map and Register Denition 2.3.1 Module Memory Map Figure 2-2. Flash Memory Map Table 2-2. Flash Register Map 2.3.2 Register Descriptions Figure 2-3. FTX512K4 Register Summary 2.3.2.1 Flash Clock Divider Register (FCLKDIV) Figure 2-3. FTX512K4 Register Summary (continued) The FCLKDIV register is used to control timed events in program and erase algorithms. All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. Figure 2-4. Flash Clock Divider Register (FCLKDIV) Table 2-3. FCLKDIV Field Descriptions 2.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. The security function in the Flash module is described in Section 2.6, Flash Module Security. Figure 2-5. Flash Security Register (FSEC) Table 2-4. FSEC Field Descriptions Table 2-5. Flash KEYEN States 2.3.2.3 Flash Test Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. Figure 2-6. Flash Test Mode Register (FTSTMOD Normal Mode) Figure 2-7. Flash Test Mode Register (FTSTMOD Special Mode) Table 2-7. FTSTMOD Field Descriptions Table 2-8. FTSTMOD Margin Read Settings 2.3.2.4 Flash Conguration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor writes. Figure 2-8. Flash Conguration Register (FCNFG Normal Mode) Figure 2-9. Flash Conguration Register (FCNFG Special Mode) Table 2-9. FCNFG Field Descriptions 2.3.2.5 Flash Protection Register (FPROT) Table 2-12. Flash Protection Function Table 2-13. Flash Protection Higher Address Range Table 2-14. Flash Protection Lower Address Range Table 2-11. FPROT Field Descriptions (continued) Page Page 2.3.2.6 Flash Status Register (FSTAT) Figure 2-13. Flash Status Register (FSTAT Special Mode) The FSTAT register defines the operational status of the module. Table 2-15. Flash Protection Scenario Transitions Figure 2-12. Flash Status Register (FSTAT Normal Mode) Table 2-16. FSTAT Field Descriptions 2.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. Figure 2-15. Flash Control Register (FCTL) The FCTL register is the Flash control register. 2.3.2.8 Flash Control Register (FCTL) 2.3.2.9 Flash Address Registers (FADDR) 2.3.2.10 Flash Data Registers (FDATA) 2.3.2.11 RESERVED1 2.3.2.12 RESERVED2 2.3.2.13 RESERVED3 2.3.2.14 RESERVED4 Figure 2-23. RESERVED4 Figure 2-21. RESERVED2 Figure 2-22. RESERVED3 2.4 Functional Description 2.4.1 Flash Command Operations 2.4.1.1 Writing the FCLKDIV Register Page Figure 2-24. Determination Procedure for PRDIV8 and FDIV Bits 2.4.1.2 Command Write Sequence 2.4.2 Flash Commands Table 2-20. Flash Command Description 2.4.2.1 Erase Verify Command Figure 2-25. Example Erase Verify Command Flow 2.4.2.2 Data Compress Command Figure 2-26. Example Data Compress Command Flow Page 2.4.2.3 Program Command Figure 2-28. Example Program Command Flow 2.4.2.4 Sector Erase Command Figure 2-29. Example Sector Erase Command Flow 2.4.2.5 Mass Erase Command Figure 2-30. Example Mass Erase Command Flow 2.4.2.6 Sector Erase Abort Command Figure 2-31. Example Sector Erase Abort Command Flow 2.4.3 Illegal Flash Operations 2.5 Operating Modes 2.5.1 Wait Mode 2.5.2 Stop Mode 2.5.3 Background Debug Mode 2.6 Flash Module Security 2.6.1 Unsecuring the MCU using Backdoor Key Access 2.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM 2.7 Resets 2.7.1 Flash Reset Sequence 2.7.2 Reset While Flash Command Active 2.8 Interrupts 2.8.1 Description of Flash Interrupt Operation Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2) 3.1 Introduction 3.1.1 Glossary 3.1.2 Features 3.1.3 Modes of Operation 3.2 External Signal Description 3.3 Memory Map and Register Denition 3.3.1 Module Memory Map Table 3-2. EEPROM Register Map 3.3.2 Register Descriptions Figure 3-1. MC9S12XDP512 Register Summary 3.3.2.1 EEPROM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed events in program and erase algorithms. All bits in the ECLKDIV register are readable, bits 60 are write once and bit 7 is not writable. 3.3.2.2 RESERVED1 Figure 3-3. RESERVED1 3.3.2.3 RESERVED2 Figure 3-2. EEPROM Clock Divider Register (ECLKDIV) Table 3-3. ECLKDIV Field Descriptions 3.3.2.4 EEPROM Conguration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable. Figure 3-4. RESERVED2 Figure 3-5. EEPROM Conguration Register (ECNFG) Table 3-4. ECNFG Field Descriptions 3.3.2.5 EEPROM Protection Register (EPROT) 3.3.2.6 EEPROM Status Register (ESTAT) The ESTAT register denes the operational status of the module. Figure 3-8. EEPROM Status Register (ESTAT Special Mode) Table 3-6. EEPROM Protection Address Range Figure 3-7. EEPROM Status Register (ESTAT Normal Mode) Table 3-7. ESTAT Field Descriptions 3.3.2.7 EEPROM Command Register (ECMD) The ECMD register is the EEPROM command register. Figure 3-10. RESERVED3 3.3.2.8 RESERVED3 Figure 3-9. EEPROM Command Register (ECMD) Table 3-8. ECMD Field Descriptions 3.3.2.9 EEPROM Data Registers (EDATA) 3.4 Functional Description 3.4.1 EEPROM Command Operations 3.4.1.1 Writing the ECLKDIV Register Page Figure 3-14. Determination Procedure for PRDIV8 and EDIV Bits 3.4.1.2 Command Write Sequence 3.4.2 EEPROM Commands Table 3-10. EEPROM Command Description 3.4.2.1 Erase Verify Command Figure 3-15. Example Erase Verify Command Flow 3.4.2.2 Program Command Figure 3-16. Example Program Command Flow 3.4.2.3 Sector Erase Command Figure 3-17. Example Sector Erase Command Flow 3.4.2.4 Mass Erase Command Figure 3-18. Example Mass Erase Command Flow 3.4.2.5 Sector Erase Abort Command Figure 3-19. Example Sector Erase Abort Command Flow 3.4.2.6 Sector Modify Command Figure 3-20. Example Sector Modify Command Flow 3.4.3 Illegal EEPROM Operations 3.5 Operating Modes 3.5.1 Wait Mode 3.5.2 Stop Mode 3.5.3 Background Debug Mode 3.6 EEPROM Module Security 3.7 Resets 3.7.1 EEPROM Reset Sequence 3.7.2 Reset While EEPROM Command Active 3.8 Interrupts 3.8.1 Description of EEPROM Interrupt Operation Chapter 4 Port Integration Module (S12XDP512PIMV2) 4.1 Introduction 4.1.1 Features 4.1.2 Block Diagram Figure 4-1. MC9S12XDP512 Block Diagram Port T ECLK Port Integration Module RXD SCI4 SPI1 SPI2 4.2 External Signal Description This section lists and describes the signals that do connect off-chip. 4.2.1 Signal Properties Table 4-1. Pin Functions and Priorities (Sheet 1 of 7) Table 4-1. Pin Functions and Priorities (Sheet 2 of 7) Table 4-1. Pin Functions and Priorities (Sheet 3 of 7) Table 4-1. Pin Functions and Priorities (Sheet 4 of 7) Table 4-1. Pin Functions and Priorities (Sheet 5 of 7) Table 4-1. Pin Functions and Priorities (Sheet 6 of 7) Table 4-1. Pin Functions and Priorities (Sheet 7 of 7) 4.3 Memory Map and Register Denition This section provides a detailed description of all MC9S12XDP512 registers. 4.3.1 Module Memory Map Table 4-2 shows the register map of the port integration module. Table 4-2. PIM Memory Map (Sheet 1 of 3) Table 4-2. PIM Memory Map (Sheet 2 of 3) Table 4-2. PIM Memory Map (Sheet 3 of 3) 4.3.2 Register Descriptions Figure 4-2. PIM Register Summary (Sheet 1 of 6) Figure 4-2. PIM Register Summary (Sheet 2 of 6) Figure 4-2. PIM Register Summary (Sheet 3 of 6) Figure 4-2. PIM Register Summary (Sheet 4 of 6) Figure 4-2. PIM Register Summary (Sheet 5 of 6) Figure 4-2. PIM Register Summary (Sheet 6 of 6) 4.3.2.1 Port A Data Register (PORTA) 4.3.2.2 Port B Data Register (PORTB) Figure 4-4. Port B Data Register (PORTB) Figure 4-3. Port A Data Register (PORTA) Table 4-4. PORTA Field Descriptions Table 4-5. PORTB Field Descriptions 4.3.2.3 Port A Data Direction Register (DDRA) 4.3.2.4 Port B Data Direction Register (DDRB) Figure 4-6. Port B Data Direction Register (DDRB) Figure 4-5. Port A Data Direction Register (DDRA) Table 4-6. DDRA Field Descriptions Table 4-7. DDRB Field Descriptions 4.3.2.5 Port C Data Register (PORTC) 4.3.2.6 Port D Data Register (PORTD) Figure 4-7. Port C Data Register (PORTC) Table 4-8. PORTC Field Descriptions Figure 4-8. Port D Data Register (PORTD) Table 4-9. PORTD Field Descriptions 4.3.2.7 Port C Data Direction Register (DDRC) 4.3.2.8 Port D Data Direction Register (DDRD) Figure 4-10. Port D Data Direction Register (DDRD) Figure 4-9. Port C Data Direction Register (DDRC) Table 4-10. DDRC Field Descriptions Table 4-11. DDRD Field Descriptions 4.3.2.9 Port E Data Register (PORTE) Figure 4-11. Port E Data Register (PORTE) Table 4-12. PORTE Field Descriptions 4.3.2.10 Port E Data Direction Register (DDRE) Figure 4-12. Port E Data Direction Register (DDRE) Table 4-13. DDRE Field Descriptions 4.3.2.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Figure 4-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Table 4-14. PUCR Field Descriptions 4.3.2.12 S12X_EBI Ports Reduced Drive Register (RDRIV) Figure 4-14. S12X_EBI Ports Reduced Drive Register (RDRIV) Table 4-15. RDRIV Field Descriptions 4.3.2.13 ECLK Control Register (ECLKCTL) Figure 4-15. ECLK Control Register (ECLKCTL) Table 4-16. ECLKCTL Field Descriptions 4.3.2.14 IRQ Control Register (IRQCR) Read: See individual bit descriptions below. Write: See individual bit descriptions below. Table 4-17. Free-Running ECLK Clock Rate Figure 4-16. IRQ Control Register (IRQCR) Table 4-16. ECLKCTL Field Descriptions (continued) Table 4-18. IRQCR Field Descriptions 4.3.2.15 Port K Data Register (PORTK) 4.3.2.16 Port K Data Direction Register (DDRK) Figure 4-18. Port K Data Direction Register (DDRK) Figure 4-17. Port K Data Register (PORTK) Table 4-19. PORTK Field Descriptions Table 4-20. DDRK Field Descriptions 4.3.2.17 Port T Data Register (PTT) 4.3.2.18 Port T Input Register (PTIT) Write: Never, writes to this register have no effect. Figure 4-19. Port T Data Register (PTT) Table 4-21. PTT Field Descriptions Figure 4-20. Port T Input Register (PTIT) 4.3.2.19 Port T Data Direction Register (DDRT) 4.3.2.20 Port T Reduced Drive Register (RDRT) 4.3.2.21 Port T Pull Device Enable Register (PERT) 4.3.2.22 Port T Polarity Select Register (PPST) 4.3.2.23 Port S Data Register (PTS) Page 4.3.2.24 Port S Input Register (PTIS) 4.3.2.25 Port S Data Direction Register (DDRS) 4.3.2.26 Port S Reduced Drive Register (RDRS) 4.3.2.27 Port S Pull Device Enable Register (PERS) 4.3.2.28 Port S Polarity Select Register (PPSS) 4.3.2.29 Port S Wired-OR Mode Register (WOMS) 4.3.2.30 Port M Data Register (PTM) Figure 4-32. Port M Data Register (PTM) Table 4-32. PTM Field Descriptions Table 4-32. PTM Field Descriptions (continued) 4.3.2.31 Port M Input Register (PTIM) 4.3.2.32 Port M Data Direction Register (DDRM) 4.3.2.33 Port M Reduced Drive Register (RDRM) 4.3.2.34 Port M Pull Device Enable Register (PERM) 4.3.2.35 Port M Polarity Select Register (PPSM) 4.3.2.36 Port M Wired-OR Mode Register (WOMM) Table 4-37. WOMM Field Descriptions 4.3.2.37 Module Routing Register (MODRR) This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Figure 4-39. Module Routing Register (MODRR) Table 4-38. Module Routing Summary 4.3.2.38 Port P Data Register (PTP) 4.3.2.39 Port P Input Register (PTIP) 4.3.2.40 Port P Data Direction Register (DDRP) 4.3.2.41 Port P Reduced Drive Register (RDRP) 4.3.2.42 Port P Pull Device Enable Register (PERP) 4.3.2.43 Port P Polarity Select Register (PPSP) 4.3.2.44 Port P Interrupt Enable Register (PIEP) Table 4-43. PIEP Field Descriptions 4.3.2.45 Port P Interrupt Flag Register (PIFP) 4.3.2.46 Port H Data Register (PTH) 4.3.2.47 Port H Input Register (PTIH) 4.3.2.48 Port H Data Direction Register (DDRH) 4.3.2.49 Port H Reduced Drive Register (RDRH) 4.3.2.50 Port H Pull Device Enable Register (PERH) 4.3.2.51 Port H Polarity Select Register (PPSH) 4.3.2.52 Port H Interrupt Enable Register (PIEH) Table 4-49. PIEH Field Descriptions 4.3.2.53 Port H Interrupt Flag Register (PIFH) 4.3.2.54 Port J Data Register (PTJ) Figure 4-56. Port J Data Register (PTJ) Table 4-51. PTJ Field Descriptions Table 4-51. PTJ Field Descriptions (continued) 4.3.2.55 Port J Input Register (PTIJ) 4.3.2.56 Port J Data Direction Register (DDRJ) 4.3.2.57 Port J Reduced Drive Register (RDRJ) 4.3.2.58 Port J Pull Device Enable Register (PERJ) Table 4-54. PERJ Field Descriptions 4.3.2.59 Port J Polarity Select Register (PPSJ) Figure 4-62. Port J Interrupt Enable Register (PIEJ) 4.3.2.60 Port J Interrupt Enable Register (PIEJ) Figure 4-61. Port J Polarity Select Register (PPSJ) Table 4-55. PPSJ Field Descriptions Table 4-56. PIEJ Field Descriptions 4.3.2.61 Port J Interrupt Flag Register (PIFJ) 4.3.2.62 Port AD0 Data Register 1 (PT1AD0) 4.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0) This register configures pins PAD[07:00] as either input or output. Figure 4-65. Port AD0 Data Direction Register 1 (DDR1AD0) Table 4-58. DDR1AD0 Field Descriptions 4.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0) 4.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0) 4.3.2.66 Port AD1 Data Register 0 (PT0AD1) 4.3.2.67 Port AD1 Data Register 1 (PT1AD1) 4.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1) This register configures pin PAD[23:16] as either input or output. Figure 4-70. Port AD1 Data Direction Register 0 (DDR0AD1) Table 4-61. DDR0AD1 Field Descriptions 4.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1) This register configures pins PAD[15:08] as either input or output. Figure 4-71. Port AD1 Data Direction Register 1 (DDR1AD1) Table 4-62. DDR1AD1 Field Descriptions 4.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1) 4.3.2.71 Port AD1 Reduced Drive Register 1 (RDR1AD1) 4.3.2.72 Port AD1 Pull Up Enable Register 0 (PER0AD1) 4.3.2.73 Port AD1 Pull Up Enable Register 1 (PER1AD1) 4.4 Functional Description 4.4.1 Registers 4.4.1.1 Data Register 4.4.1.2 Input Register 4.4.1.3 Data Direction Register 4.4.1.4 Reduced Drive Register 4.4.1.5 Pull Device Enable Register 4.4.1.6 Polarity Select Register 4.4.2 Ports 4.4.2.1 BKGD Pin 4.4.2.2 Port A and B 4.4.2.3 Port C and D 4.4.2.4 Port E 4.4.2.5 Port K 4.4.2.6 Port T 4.4.2.7 Port S 4.4.2.8 Port M 4.4.2.9 Port P 4.4.2.10 Port H 4.4.2.11 Port J 4.4.2.12 Port AD0 4.4.2.13 Port AD1 4.4.3 Pin Interrupts 4.4.4 Expanded Bus Pin Functions Table 4-70. Expanded Bus Pin Functions versus Operating Modes 4.4.5 Low-Power Options 4.4.5.1 Run Mode No low-power options exist for this module in run mode. 4.5 Initialization and Application Information Table 4-70. Expanded Bus Pin Functions versus Operating Modes (continued) Page Page Chapter 5 Clocks and Reset Generator (S12CRGV6) 5.1 Introduction 5.1.1 Features 5.1.2 Modes of Operation 5.1.3 Block Diagram Clock and Reset Control 5.2 External Signal Description 5.2.1 VDDPLL and VSSPLL Operating and Ground Voltage Pins 5.2.2 XFC External Loop Filter Pin 5.2.3 RESET Reset Pin 5.3 Memory Map and Register Denition 5.3.1 Module Memory Map Table 5-1 gives an overview on all MC9S12XDP512 registers. Table 5-1. MC9S12XDP512 Memory Map 5.3.2 Register Descriptions This section describes in address order all the MC9S12XDP512 registers and their individual bits. Figure 5-3. S12CRGV6 Register Summary 5.3.2.1 CRG Synthesizer Register (SYNR) 5.3.2.2 CRG Reference Divider Register (REFDV) 5.3.2.3 Reserved Register (CTFLG) 5.3.2.4 CRG Flags Register (CRGFLG) Table 5-2. CRGFLG Field Descriptions 5.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. Figure 5-8. CRG Interrupt Enable Register (CRGINT) Table 5-3. CRGINT Field Descriptions 5.3.2.6 CRG Clock Select Register (CLKSEL) Write: Refer to each bit for individual write conditions Figure 5-9. CRG Clock Select Register (CLKSEL) Table 5-4. CLKSEL Field Descriptions 5.3.2.7 CRG PLL Control Register (PLLCTL) This register controls the PLL functionality. Write: Refer to each bit for individual write conditions Figure 5-10. CRG PLL Control Register (PLLCTL) Table 5-5. PLLCTL Field Descriptions 5.3.2.8 CRG RTI Control Register (RTICTL) This register selects the timeout period for the real time interrupt. A write to this register initializes the RTI counter. Figure 5-11. CRG RTI Control Register (RTICTL) Table 5-6. RTICTL Field Descriptions Table 5-7. RTI Frequency Divide Rates for RTDEC = 0 Table 5-8. RTI Frequency Divide Rates for RTDEC = 1 5.3.2.9 CRG COP Control Register (COPCTL) T able 5-10. COP W atchdog Rates Table 5-9. COPCTL Field Descriptions (continued) 5.3.2.10 Reserved Register (FORBYP) 5.3.2.11 Reserved Register (CTCTL) 5.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) 5.4 Functional Description 5.4.1 Functional Blocks 5.4.1.1 Phase Locked Loop (PLL) Page 5.4.1.2 System Clocks Generator 5.4.1.3 Clock Monitor (CM) 5.4.1.4 Clock Quality Checker Figure 5-19. Check Window Example Figure 5-20. Sequence for Clock Quality Check The sequence for clock quality check is shown in Figure 5-20. 5.4.1.5 Computer Operating Properly Watchdog (COP) 5.4.1.6 Real Time Interrupt (RTI) 5.4.2 Operating Modes 5.4.2.1 Normal Mode 5.4.2.2 Self Clock Mode 5.4.3 Low Power Options 5.4.3.1 Run Mode 5.4.3.2 Wait Mode Figure 5-21. Wait Mode Entry/Exit Sequence 5.4.3.3 System Stop Mode Table 5-12. Outcome of Clock Loss in Wait Mode Chapter 5 Clocks and Reset Generator (S12CRGV6) Figure 5-22. Stop Mode Entry/Exit Sequence Page Table 5-13. Outcome of Clock Loss in Pseudo Stop Mode Page Power Saving CPU resumes program execution immediately 5.5 Resets 5.5.1 Description of Reset Operation Figure 5-25. RESET Timing Table 5-15. Reset Vector Selection ) ( ) ( 5.5.2 Clock Monitor Reset 5.5.3 Computer Operating Properly Watchdog (COP) Reset 5.5.4 Power On Reset, Low Voltage Reset 308 Freescale Semiconductor Figure 5-26. RESET Pin Tied to VDD (by a pull-up resistor) 5.6 Interrupts 5.6.1 Real Time Interrupt Table 5-16. CRG Interrupt Vectors 5.6.2 PLL Lock Interrupt 5.6.3 Self Clock Mode Interrupt Page Chapter 6 Pierce Oscillator (S12XOSCLCPV1) 6.1 Introduction 6.1.1 Features 6.1.2 Modes of Operation 6.1.3 Block Diagram 6.2 External Signal Description 6.2.1 VDDPLL and VSSPLL Operating and Ground Voltage Pins 6.2.2 EXTAL and XTAL Input and Output Pins Page 6.2.3 XCLKS Input Signal 6.3 Memory Map and Register Denition 6.4 Functional Description 6.4.1 Gain Control 6.4.2 Clock Monitor Page Page Chapter 7 Analog-to-Digital Converter (ATD10B16CV4) 7.1 Introduction 7.1.1 Features 7.1.2 Modes of Operation 7.1.3 Block Diagram Figure 7-1. ATD10B16C Block Diagram 7.2 External Signal Description 7.3 Memory Map and Register Denition Table 7-1. MC9S12XDP512 Memory Map 7.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits. Figure 7-2. ATD Register Summary 7.3.2.1 ATD Control Register 0 (ATDCTL0) Figure 7-2. ATD Register Summary (continued) Figure 7-3. ATD Control Register 0 (ATDCTL0) Table 7-2. ATDCTL0 Field Descriptions 7.3.2.2 ATD Control Register 1 (ATDCTL1) Table 7-3. Multi-Channel Wrap Around Coding Figure 7-4. ATD Control Register 1 (ATDCTL1) Table 7-4. ATDCTL1 Field Descriptions 7.3.2.3 ATD Control Register 2 (ATDCTL2) Table 7-5. External Trigger Channel Select Coding Figure 7-5. ATD Control Register 2 (ATDCTL2) Table 7-6. ATDCTL2 Field Descriptions Table 7-7. External Trigger Congurations Table 7-6. ATDCTL2 Field Descriptions (continued) 7.3.2.4 ATD Control Register 3 (ATDCTL3) Figure 7-6. ATD Control Register 3 (ATDCTL3) Table 7-8. ATDCTL3 Field Descriptions Table 7-9. Conversion Sequence Length Coding Table 7-10. ATD Behavior in Freeze Mode (Breakpoint) 7.3.2.5 ATD Control Register 4 (ATDCTL4) Figure 7-7. ATD Control Register 4 (ATDCTL4) Table 7-11. ATDCTL4 Field Descriptions Table 7-12. Sample Time Select Table 7-13. Clock Prescaler Values 7.3.2.6 ATD Control Register 5 (ATDCTL5) Figure 7-8. ATD Control Register 5 (ATDCTL5) Table 7-14. ATDCTL5 Field Descriptions Table 7-15. Available Result Data Formats. Table 7-16. Left Justied, Signed and Unsigned ATD Output Codes. Table 7-14. ATDCTL5 Field Descriptions (continued) Table 7-17. Analog Input Channel Select Coding 7.3.2.7 ATD Status Register 0 (ATDSTAT0) Write: Anytime (No effect on CC[3:0]) Figure 7-9. ATD Status Register 0 (ATDSTAT0) Table 7-18. ATDSTAT0 Field Descriptions 7.3.2.8 Reserved Register 0 (ATDTEST0) 7.3.2.9 ATD Test Register 1 (ATDTEST1) 7.3.2.10 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8. Table 7-20. Special Channel Select Coding Figure 7-12. ATD Status Register 2 (ATDSTAT2) Table 7-21. ATDSTAT2 Field Descriptions 7.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 Figure 7-13. ATD Status Register 1 (ATDSTAT1) Table 7-22. ATDSTAT1 Field Descriptions 7.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) 7.3.2.13 ATD Input Enable Register 1 (ATDDIEN1) Figure 7-14. ATD Input Enable Register 0 (ATDDIEN0) Table 7-23. ATDDIEN0 Field Descriptions Figure 7-15. ATD Input Enable Register 1 (ATDDIEN1) Table 7-24. ATDDIEN1 Field Descriptions 7.3.2.14 Port Data Register 0 (PORTAD0) The A/D input channels may be used for general-purpose digital input. Figure 7-16. Port Data Register 0 (PORTAD0) Table 7-25. PORTAD0 Field Descriptions 7.3.2.15 Port Data Register 1 (PORTAD1) The A/D input channels may be used for general-purpose digital input. Figure 7-17. Port Data Register 1 (PORTAD1) Table 7-26. PORTAD1 Field Descriptions 7.3.2.16 ATD Conversion Result Registers (ATDDRx) Figure 7-19. Left Justied, ATD Conversion Result Register x, Low Byte (ATDDRxL) Write: Anytime in special mode, unimplemented in normal modes 7.3.2.16.1 Left Justied Result Data Figure 7-18. Left Justied, ATD Conversion Result Register x, High Byte (ATDDRxH) 7.3.2.16.2 Right Justied Result Data 7.4 Functional Description The ATD10B16C is structured in an analog and a digital sub-block. 7.4.1 Analog Sub-block 7.4.1.1 Sample and Hold Machine Figure 7-20. Right Justied, ATD Conversion Result Register x, High Byte (ATDDRxH) 7.4.2 Digital Sub-Block 7.4.2.1 External Trigger Input 7.4.2.2 General-Purpose Digital Input Port Operation 7.4.3 Operation in Low Power Modes 7.5 Resets 7.6 Interrupts Page Chapter 8 Analog-to-Digital Converter (ATD10B8CV3) 8.1 Introduction 8.1.1 Features 8.1.2 Modes of Operation 8.1.2.1 Conversion Modes 8.2 External Signal Description 8.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) Analog Input Pin 8.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 External Trigger Pins 8.2.3 VRH and VRL High and Low Reference Voltage Pins 8.2.4 V Figure 8-1. ATD Block Diagram ATD10B8C 8.3 Memory Map and Register Denition This section provides a detailed description of all registers accessible in the ATD. Figure 8-2. ATD Register Summary (Sheet 1 of 5) 8.3.1 Module Memory Map Figure 8-2 gives an overview of all ATD registers. Figure 8-2. ATD Register Summary (Sheet 2 of 5) Figure 8-2. ATD Register Summary (Sheet 3 of 5) Figure 8-2. ATD Register Summary (Sheet 4 of 5) 8.3.2.1 ATD Control Register 0 (ATDCTL0) Figure 8-2. ATD Register Summary (Sheet 5 of 5) Figure 8-3. ATD Control Register 0 (ATDCTL0) Table 8-1. ATDCTL0 Field Descriptions Table 8-2. Multi-Channel Wrap Around Coding Page 8.3.2.2 ATD Control Register 1 (ATDCTL1) Figure 8-4. ATD Control Register 1 (ATDCTL1) Table 8-3. ATDCTL1 Field Descriptions Table 8-4. External Trigger Channel Select Coding 8.3.2.3 ATD Control Register 2 (ATDCTL2) Figure 8-5. ATD Control Register 2 (ATDCTL2) Table 8-5. ATDCTL2 Field Descriptions 8.3.2.4 ATD Control Register 3 (ATDCTL3) Table 8-6. External Trigger Congurations Figure 8-6. ATD Control Register 3 (ATDCTL3) Table 8-7. ATDCTL3 Field Descriptions Table 8-5. ATDCTL2 Field Descriptions (continued) Table 8-8. Conversion Sequence Length Coding Table 8-9. ATD Behavior in Freeze Mode (Breakpoint) Table 8-7. ATDCTL3 Field Descriptions (continued) 8.3.2.5 ATD Control Register 4 (ATDCTL4) Figure 8-7. ATD Control Register 4 (ATDCTL4) Table 8-10. ATDCTL4 Field Descriptions Table 8-11. Sample Time Select Table 8-12. Clock Prescaler Values 8.3.2.6 ATD Control Register 5 (ATDCTL5) Figure 8-8. ATD Control Register 5 (ATDCTL5) Table 8-13. ATDCTL5 Field Descriptions Table 8-14. Available Result Data Formats Table 8-15. Left Justied, Signed, and Unsigned ATD Output Codes Table 8-16. Analog Input Channel Select Coding 8.3.2.7 ATD Status Register 0 (ATDSTAT0) Write: Anytime (No effect on (CC2, CC1, CC0)) Figure 8-9. ATD Status Register 0 (ATDSTAT0) Table 8-17. ATDSTAT0 Field Descriptions 8.3.2.8 Reserved Register (ATDTEST0) 8.3.2.9 ATD Test Register 1 (ATDTEST1) 8.3.2.10 ATD Status Register 1 (ATDSTAT1) This read-only register contains the conversion complete ags. Table 8-19. Special Channel Select Coding Figure 8-12. ATD Status Register 1 (ATDSTAT1) Table 8-20. ATDSTAT1 Field Descriptions 8.3.2.11 ATD Input Enable Register (ATDDIEN) 8.3.2.12 Port Data Register (PORTAD) 8.3.2.13 ATD Conversion Result Registers (ATDDRx) Figure 8-16. Left Justied, ATD Conversion Result Register, Low Byte (ATDDRxL) Write: Anytime in special mode, unimplemented in normal modes 8.3.2.13.1 Left Justied Result Data Table 8-22. PORTAD Field Descriptions Figure 8-15. Left Justied, ATD Conversion Result Register, High Byte (ATDDRxH) 8.4 Functional Description The ATD is structured in an analog and a digital sub-block. 8.4.1 Analog Sub-Block 8.4.1.1 Sample and Hold Machine Figure 8-17. Right Justied, ATD Conversion Result Register, High Byte (ATDDRxH) 8.4.2 Digital Sub-Block 8.4.2.1 External Trigger Input 8.4.2.2 General Purpose Digital Input Port Operation 8.4.2.3 Low Power Modes 8.5 Resets 8.6 Interrupts Chapter 9 XGATE (S12XGATEV2) 9.1 Introduction 9.1.1 Features 9.1.2 Modes of Operation 9.1.3 Block Diagram 9.2 External Signal Description XGATE 9.3 Memory Map and Register Denition 9.3.1 Module Memory Map Table 9-1. Module Memory Map 9.3.2 Register Descriptions Figure 9-2. XGATE Register Summary (Sheet 1 of 3) Figure 9-2. XGATE Register Summary (Sheet 2 of 3) Figure 9-2. XGATE Register Summary (Sheet 3 of 3) 9.3.2.1 XGATE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 9-3. Figure 9-3. XGATE Control Register (XGMCTL) Table 9-2. XGMCTL Field Descriptions (Sheet 1 of 3) Table 9-2. XGMCTL Field Descriptions (Sheet 2 of 3) Table 9-2. XGMCTL Field Descriptions (Sheet 3 of 3) 9.3.2.2 XGATE Channel ID Register (XGCHID) 9.3.2.3 XGATE Vector Base Address Register (XGVBR) 9.3.2.4 XGATE Channel Interrupt Flag Vector (XGIF) Figure 9-6. XGATE Channel Interrupt Flag Vector (XGIF) Page 9.3.2.5 XGATE Software Trigger Register (XGSWT) 9.3.2.6 XGATE Semaphore Register (XGSEM) 9.3.2.7 XGATE Condition Code Register (XGCCR) The XGCCR register (Figure 9-9) provides access to the RISC cores condition code register. Read: In debug mode if unsecured Write: In debug mode if unsecured Figure 9-9. XGATE Condition Code Register (XGCCR) Table 9-8. XGCCR Field Descriptions 9.3.2.8 XGATE Program Counter Register (XGPC) 9.3.2.9 XGATE Register 1 (XGR1) 9.3.2.10 XGATE Register 2 (XGR2) 9.3.2.11 XGATE Register 3 (XGR3) 9.3.2.12 XGATE Register 4 (XGR4) 9.3.2.13 XGATE Register 5 (XGR5) 9.3.2.14 XGATE Register 6 (XGR6) 9.3.2.15 XGATE Register 7 (XGR7) 9.4 Functional Description 9.4.1 XGATE RISC Core 9.4.2 Programmers Model 9.4.3 Memory Map 9.4.4 Semaphores Code Variables Code Variables Page S12X_CPU XGATE 9.4.5 Software Error Detection 9.5 Interrupts 9.5.1 Incoming Interrupt Requests 9.5.2 Outgoing Interrupt Requests 9.6 Debug Mode 9.6.1 Debug Features 9.6.2 Entering Debug Mode 9.6.3 Leaving Debug Mode 9.7 Security 9.8 Instruction Set 9.8.1 Addressing Modes 9.8.1.1 Naming Conventions 9.8.1.2 Inherent Addressing Mode (INH) 9.8.1.3 Immediate 3-Bit Wide (IMM3) 9.8.1.4 Immediate 4-Bit Wide (IMM4) 9.8.1.5 Immediate 8-Bit Wide (IMM8) 9.8.1.6 Immediate 16-Bit Wide (IMM16) 9.8.1.7 Monadic Addressing (MON) 9.8.1.8 Dyadic Addressing (DYA) 9.8.1.9 Triadic Addressing (TRI) 9.8.1.10 Relative Addressing 9-Bit Wide (REL9) 9.8.1.11 Relative Addressing 10-Bit Wide (REL10) 9.8.1.12 Index Register plus Immediate Offset (IDO5) 9.8.2 Instruction Summary and Usage 9.8.2.1 Load & Store Instructions 9.8.2.2 Logic and Arithmetic Instructions 9.8.2.3 Register Register Transfers 9.8.2.4 Shift Instructions 9.8.2.5 Bit Field Operations 9.8.2.6 Special Instructions for DMA Usage 9.8.3 Cycle Notation 9.8.4 Thread Execution 9.8.5 Instruction Glossary ADC Add with Carry ADC Code and CPU Cycles ADD Add without Carry ADD ADDH ADDL AND Logical AND AND ANDH ANDL ASR Arithmetic Shift Right ASR BCC BCS BEQ Branch if Equal BEQ BFEXT Bit Field Extract BFEXT BFFO Bit Field Find First One BFFO BFINS Bit Field Insert BFINS BFINSI Bit Field Insert and Invert BFINSI BFINSX Bit Field Insert and XNOR BFINSX BGE Branch if Greater than or Equal to Zero BGE BGT Branch if Greater than Zero BGT BHI Branch if Higher BHI BHS BITH BITL BLE Branch if Less or Equal to Zero BLE BLO BLS Branch if Lower or Same BLS BLT Branch if Lower than Zero BLT BMI Branch if Minus BMI BNE Branch if Not Equal BNE BPL Branch if Plus BPL BRA Branch Always BRA BRK Break BRK BVC Branch if Overflow Cleared BVC BVS Branch if Overflow Set BVS CMP Compare CMP CMPL COM Ones Complement COM CPC Compare with Carry CPC CPCH CSEM Clear Semaphore CSEM CSL Logical Shift Left with Carry CSL CSR Logical Shift Right with Carry CSR JA L LDB LDH LDL LDW Load Word from Memory LDW LSL Logical Shift Left LSL LSR Logical Shift Right LSR MOV Move Register Content MOV NEG Twos Complement NEG NOP No Operation NOP OR Logical OR OR ORH ORL PA R RO L RO R RT S SBC Subtract with Carry SBC SSEM Set Semaphore SSEM SEX Sign Extend Byte to Word SEX SIF Set Interrupt Flag SIF STB STW Store Word to Memory STW SUB Subtract without Carry SUB SUBH SUBL TFR Transfer from and to Special Registers TFR TST Test Register TST XNOR Logical Exclusive NOR XNOR XNORH XNORL 9.8.6 Instruction Coding Table 9-18 summarizes all XGATE instructions in the order of their machine coding. Table 9-18. Instruction Set Summary (Sheet 1 of 3) Table 9-18. Instruction Set Summary (Sheet 2 of 3) Table 9-18. Instruction Set Summary (Sheet 3 of 3) 9.9 Initialization and Application Information 9.9.1 Initialization 9.9.2 Code Example (Transmit "Hello World!" on SCI) Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Chapter 10 Security (S12X9SECV2) 10.1 Introduction 10.1.1 Features 10.1.2 Modes of Operation 10.1.3 Securing the Microcontroller Figure 10-1. Flash Options/Security Byte Table 10-1. Features Availability in Unsecure and Secure Modes 10.1.4 Operation of the Secured Microcontroller 10.1.4.1 Normal Single Chip Mode (NS) 10.1.4.2 Special Single Chip Mode (SS) 10.1.4.3 Expanded Modes (NX, ES, EX, and ST) 10.1.5 Unsecuring the Microcontroller 10.1.5.1 Unsecuring the MCU Using the Backdoor Key Access 10.1.5.2 Backdoor Key Access Sequence 10.1.6 Reprogramming the Security Bits 10.1.7 Complete Memory Erase (Special Modes) Page Page Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2) 11.1 Introduction 11.1.1 Features 11.1.2 Modes of Operation 11.1.3 Block Diagram Figure 11-1. ECT Block Diagram 11.2 External Signal Description 11.3 Memory Map and Register Denition This section provides a detailed description of all memory and registers. 11.3.1 Module Memory Map Table 11-1. MC9S12XDP512 Memory Map Table 11-1. MC9S12XDP512 Memory Map (continued) 11.3.2 Register Descriptions Figure 11-2. ECT Register Summary (Sheet 1 of 5) Figure 11-2. ECT Register Summary (Sheet 2 of 5) Figure 11-2. ECT Register Summary (Sheet 3 of 5) Figure 11-2. ECT Register Summary (Sheet 4 of 5) 11.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS) Figure 11-2. ECT Register Summary (Sheet 5 of 5) Figure 11-3. Timer Input Capture/Output Compare Register (TIOS) Table 11-2. TIOS Field Descriptions 11.3.2.2 Timer Compare Force Register (CFORC) Read or write: Anytime but reads will always return 0x0000 (1 state is transient). 11.3.2.3 Output Compare 7 Mask Register (OC7M) Figure 11-4. Timer Compare Force Register (CFORC) Table 11-3. CFORC Field Descriptions Figure 11-5. Output Compare 7 Mask Register (OC7M) Table 11-4. OC7M Field Descriptions 11.3.2.4 Output Compare 7 Data Register (OC7D) Figure 11-6. Output Compare 7 Data Register (OC7D) Table 11-5. OC7D Field Descriptions 11.3.2.5 Timer Count Register (TCNT) Figure 11-7. Timer Count Register High (TCNT) Figure 11-8. Timer Count Register Low (TCNT) Table 11-6. TCNT Field Descriptions 11.3.2.6 Timer System Control Register 1 (TSCR1) Read or write: Anytime except PRNT bit is write once Figure 11-9. Timer System Control Register 1 (TSCR1) Table 11-7. TSCR1 Field Descriptions 11.3.2.7 Timer Toggle On Overow Register 1 (TTOV) Figure 11-10. Timer Toggle On Overow Register 1 (TTOV) Table 11-8. TTOV Field Descriptions 11.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Figure 11-11. Timer Control Register 1 (TCTL1) Figure 11-12. Timer Control Register 2 (TCTL2) Table 11-9. TCTL1/TCTL2 Field Descriptions Table 11-10. Compare Result Output Action 11.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4) Figure 11-13. Timer Control Register 3 (TCTL3) Figure 11-14. Timer Control Register 4 (TCTL4) Table 11-11. TCTL3/TCTL4 Field Descriptions Table 11-12. Edge Detector Circuit Conguration 11.3.2.10 Timer Interrupt Enable Register (TIE) The bits C7IC0I correspond bit-for-bit with the ags in the TFLG1 status register. Figure 11-15. Timer Interrupt Enable Register (TIE) Table 11-13. TIE Field Descriptions 11.3.2.11 Timer System Control Register 2 (TSCR2) Figure 11-16. Timer System Control Register 2 (TSCR2) Table 11-14. TSCR2 Field Descriptions Table 11-15. Prescaler Selection 11.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) 11.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) 11.3.2.14 Timer Input Capture/Output Compare Registers 07 Figure 11-19. Timer Input Capture/Output Compare Register 0 High (TC0) Figure 11-24. Timer Input Capture/Output Compare Register 2 Low (TC2) Figure 11-20. Timer Input Capture/Output Compare Register 0 Low (TC0) Figure 11-21. Timer Input Capture/Output Compare Register 1 High (TC1) Figure 11-25. Timer Input Capture/Output Compare Register 3 High (TC3) Figure 11-26. Timer Input Capture/Output Compare Register 3 Low (TC3) Figure 11-30. Timer Input Capture/Output Compare Register 5 Low (TC5) Figure 11-27. Timer Input Capture/Output Compare Register 4 High (TC4) Figure 11-28. Timer Input Capture/Output Compare Register 4 Low (TC4) Page 11.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL) Figure 11-35. 16-Bit Pulse Accumulator Control Register (PACTL) Table 11-18. PACTL Field Descriptions 11.3.2.16 Pulse Accumulator A Flag Register (PAFLG) 11.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2) 11.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0) 11.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL) Figure 11-41. 16-Bit Modulus Down-Counter Control Register (MCCTL) Table 11-22. MCCTL Field Descriptions 11.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG) 11.3.2.21 ICPAR Input Control Pulse Accumulators Register (ICPAR) 11.3.2.22 Delay Counter Control Register (DLYCT) Figure 11-44. Delay Counter Control Register (DLYCT) Table 11-26. DLYCT Field Descriptions Table 11-27. Delay Counter Select when PRNT = 0 Table 11-28. Delay Counter Select Examples when PRNT = 1 11.3.2.23 Input Control Overwrite Register (ICOVW) Figure 11-45. Input Control Overwrite Register (ICOVW) Table 11-29. ICOVW Field Descriptions Table 11-28. Delay Counter Select Examples when PRNT = 1 11.3.2.24 Input Control System Control Register (ICSYS) Write: Once in normal modes Figure 11-46. Input Control System Register (ICSYS) Table 11-30. ICSYS Field Descriptions 11.3.2.25 Precision Timer Prescaler Select Register (PTPSR) Table 11-32. Precision Timer Prescaler Selection Examples when PRNT = 1 Table 11-30. ICSYS Field Descriptions (continued) 11.3.2.26 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) Figure 11-48. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) Table 11-33. PTMCPSR Field Descriptions Table 11-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 Table 11-32. Precision Timer Prescaler Selection Examples when PRNT = 1 11.3.2.27 16-Bit Pulse Accumulator B Control Register (PBCTL) Figure 11-49. 16-Bit Pulse Accumulator B Control Register (PBCTL) Table 11-35. PBCTL Field Descriptions Table 11-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued) 11.3.2.28 Pulse Accumulator B Flag Register (PBFLG) 11.3.2.29 8-Bit Pulse Accumulators Holding Registers (PA3HPA0H) Write: Has no effect. Figure 11-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H) Figure 11-54. 8-Bit Pulse Accumulators Holding Register 0 (PA0H) Figure 11-52. 8-Bit Pulse Accumulators Holding Register 2 (PA2H) 11.3.2.30 Modulus Down-Counter Count Register (MCCNT) 11.3.2.31 Timer Input Capture Holding Registers 03 (TCxH) Figure 11-57. Timer Input Capture Holding Register 0 High (TC0H) Figure 11-61. Timer Input Capture Holding Register 2 High (TC2H) Figure 11-58. Timer Input Capture Holding Register 0 Low (TC0H) Figure 11-59. Timer Input Capture Holding Register 1 High (TC1H) 11.4 Functional Description Figure 11-65. Detailed Timer Block Diagram in Latch Mode when PRNT = 0 Figure 11-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 1 Figure 11-67. Detailed Timer Block Diagram in Queue Mode when PRNT = 0 Figure 11-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 1 Figure 11-69. 8-Bit Pulse Accumulators Block Diagram Figure 11-70. 16-Bit Pulse Accumulators Block Diagram Figure 11-71. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A 11.4.1 Enhanced Capture Timer Modes of Operation 11.4.1.1 IC Channels Page 11.4.1.2 OC Channel Initialization 11.4.1.3 Pulse Accumulators 11.4.1.4 Modulus Down-Counter 11.4.1.5 Precision Timer 11.4.1.6 Flag Clearing Mechanisms 11.4.2 Reset 11.4.3 Interrupts 11.4.3.1 Channel [7:0] Interrupt 11.4.3.2 Modulus Counter Interrupt 11.4.3.3 Pulse Accumulator B Overow Interrupt 11.4.3.4 Pulse Accumulator A Input Interrupt Page Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1) 12.1 Introduction 12.1.1 Features 12.1.2 Modes of Operation 12.1.3 Block Diagram 12.2 External Signal Description The PWM module has a total of 8 external pins. 12.2.1 PWM7 PWM Channel 7 12.2.2 PWM6 PWM Channel 6 PWM8B8C 12.3 Memory Map and Register Denition 12.3.2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module. Figure 12-2. PWM Register Summary (Sheet 1 of 3) Figure 12-2. PWM Register Summary (Sheet 2 of 3) 12.3.2.1 PWM Enable Register (PWME) Figure 12-2. PWM Register Summary (Sheet 3 of 3) The rst PWM cycle after enabling the channel can be irregular. Figure 12-3. PWM Enable Register (PWME) Table 12-1. PWME Field Descriptions 12.3.2.2 PWM Polarity Register (PWMPOL) 12.3.2.3 PWM Clock Select Register (PWMCLK) 12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK) This register selects the prescale clock source for clocks A and B independently. Figure 12-5. PWM Clock Select Register (PWMCLK) Table 12-3. PWMCLK Field Descriptions Figure 12-6. PWM Prescale Clock Select Register (PWMPRCLK) Table 12-4. PWMPRCLK Field Descriptions Table 12-5. Clock B Prescaler Selects Table 12-6. Clock A Prescaler Selects 12.3.2.5 PWM Center Align Enable Register (PWMCAE) 12.3.2.6 PWM Control Register (PWMCTL) Change these bits only when both corresponding channels are disabled. Table 12-8. PWMCTL Field Descriptions 12.3.2.7 Reserved Register (PWMTST) 12.3.2.8 Reserved Register (PWMPRSC) 12.3.2.9 PWM Scale A Register (PWMSCLA) 12.3.2.10 PWM Scale B Register (PWMSCLB) 12.3.2.11 Reserved Registers (PWMSCNTx) 12.3.2.12 PWM Channel Counter Registers (PWMCNTx) 12.3.2.13 PWM Channel Period Registers (PWMPERx) 12.3.2.14 PWM Channel Duty Registers (PWMDTYx) 12.3.2.15 PWM Shutdown Register (PWMSDN) Figure 12-17. PWM Shutdown Register (PWMSDN) Table 12-9. PWMSDN Field Descriptions 12.4 Functional Description 12.4.1 PWM Clock Select 12.4.1.1 Prescale 12.4.1.2 Clock Scale Figure 12-18. PWM Clock Select Block Diagram 12.4.1.3 Clock Select 12.4.2 PWM Channel Timers 12.4.2.1 PWM Enable 12.4.2.2 PWM Polarity 12.4.2.3 PWM Period and Duty 12.4.2.4 PWM Timer Counters 12.4.2.5 Left Aligned Outputs Page 12.4.2.6 Center Aligned Outputs Page 12.4.2.7 PWM 16-Bit Functions Page 12.4.2.8 PWM Boundary Cases 12.5 Resets 12.6 Interrupts Page Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description 13.1 Introduction 13.1.1 Features 13.1.2 Modes of Operation SDA 13.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 13-1. 13.2 External Signal Description 13.2.1 IIC_SCL Serial Clock Line Pin 13.2.2 IIC_SDA Serial Data Line Pin 13.3 Memory Map and Register Denition 13.3.1 Module Memory Map 13.3.2 Register Descriptions 13.3.2.1 IIC Address Register (IBAD) Figure 13-3. IIC Bus Address Register (IBAD) Figure 13-2. IIC Register Summary 13.3.2.2 IIC Frequency Divider Register (IBFD) Table 13-2. IBAD Field Descriptions Figure 13-4. IIC Bus Frequency Divider Register (IBFD) Table 13-3. IBFD Field Descriptions Table 13-4. I-Bus Tap and Prescale Values Table 13-5. Multiplier Factor Figure 13-5. SCL Divider and SDA Hold Table 13-6. IIC Divider and Hold Values (Sheet 1 of 5) MUL=1 Table 13-6. IIC Divider and Hold Values (Sheet 2 of 5) MUL=2 Table 13-6. IIC Divider and Hold Values (Sheet 3 of 5) MUL=4 Table 13-6. IIC Divider and Hold Values (Sheet 4 of 5) Table 13-6. IIC Divider and Hold Values (Sheet 5 of 5) 13.3.2.3 IIC Control Register (IBCR) Figure 13-6. IIC Bus Control Register (IBCR) Table 13-7. IBCR Field Descriptions 13.3.2.4 IIC Status Register (IBSR) Table 13-8. IBSR Field Descriptions (continued) 13.3.2.5 IIC Data I/O Register (IBDR) 13.4 Functional Description 13.4.1 I-Bus Protocol 608 Freescale Semiconductor Figure 13-9. IIC-Bus Transmission Signals 13.4.1.1 START Signal Figure 13-10. Start and Stop Conditions SDA SCL START Condition STOP Condition 13.4.1.2 Slave Address Transmission 13.4.1.3 Data Transfer 13.4.1.4 STOP Signal 13.4.1.5 Repeated START Signal 13.4.1.6 Arbitration Procedure 13.4.1.7 Clock Synchronization 13.4.1.8 Handshaking 13.4.1.9 Clock Stretching 13.5 Resets 13.6 Interrupts 13.7 Initialization/Application Information 13.7.1 IIC Programming Examples 13.7.1.1 Initialization Sequence 13.7.1.2 Generation of START 13.7.1.3 Post-Transfer Software Response 13.7.1.4 Generation of STOP 13.7.1.5 Generation of Repeated START 13.7.1.6 Slave Mode 13.7.1.7 Arbitration Lost Figure 13-12. Flow-Chart of Typical IIC Interrupt Routine Page Chapter 14 Freescales Scalable Controller Area Network (S12MSCANV3) 14.1 Introduction 14.1.1 Glossary 14.1.2 Block Diagram 14.1.3 Features MSCAN 14.1.4 Modes of Operation 14.2 External Signal Description 14.2.1 RXCAN CAN Receiver Input Pin 14.2.2 TXCAN CAN Transmitter Output Pin 14.2.3 CAN System 14.3 Memory Map and Register Denition 14.3.1 Module Memory Map Table 14-1. MSCAN Memory Map 14.3.2 Register Descriptions 14.3.2.1 MSCAN Control Register 0 (CANCTL0) Table 14-2. CANCTL0 Register Field Descriptions (continued) 14.3.2.2 MSCAN Control Register 1 (CANCTL1) Figure 14-4. MSCAN Control Register 1 (CANCTL1) Table 14-3. CANCTL1 Register Field Descriptions Table 14-3. CANCTL1 Register Field Descriptions (continued) 14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register congures various CAN bus timing parameters of the MSCAN module. Figure 14-5. MSCAN Bus Timing Register 0 (CANBTR0) Table 14-4. CANBTR0Register Field Descriptions Table 14-5. Synchronization Jump Width Table 14-6. Baud Rate Prescaler 14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register congures various CAN bus timing parameters of the MSCAN module. Figure 14-6. MSCAN Bus Timing Register 1 (CANBTR1) Table 14-7. CANBTR1 Register Field Descriptions Table 14-8. Time Segment 2 Values 14.3.2.5 MSCAN Receiver Flag Register (CANRFLG) Table 14-10. CANRFLG Register Field Descriptions 14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) Write: Anytime when not in initialization mode Figure 14-8. MSCAN Receiver Interrupt Enable Register (CANRIER) Table 14-11. CANRIER Register Field Descriptions 14.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) 14.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt ags. Write: Anytime when not in initialization mode Table 14-12. CANTFLG Register Field Descriptions Figure 14-10. MSCAN Transmitter Interrupt Enable Register (CANTIER) 14.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) 14.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) 14.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) 14.3.2.12 MSCAN Identier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identier acceptance control as described below. Table 14-18. Identier Acceptance Mode Settings Table 14-19. Identier Acceptance Hit Indication 14.3.2.13 MSCAN Reserved Register 14.3.2.14 MSCAN Miscellaneous Register (CANMISC) 14.3.2.15 MSCAN Receive Error Counter (CANRXERR) 14.3.2.16 MSCAN Transmit Error Counter (CANTXERR) 14.3.2.17 MSCAN Identier Acceptance Registers (CANIDAR0-7) Page 14.3.2.18 MSCAN Identier Mask Registers (CANIDMR0CANIDMR7) Page 14.3.3 Programmers Model of Message Storage Figure 14-23. Receive/Transmit Message Buffer Extended Identier Mapping 14.3.3.1 Identier Registers (IDR0IDR3) Page 14.3.3.1.2 IDR0IDR3 for Standard Identier Mapping Figure 14-30. Identier Register 1 Standard Mapping Table 14-31. IDR1 Register Field Descriptions Figure 14-31. Identier Register 2 Standard Mapping 14.3.3.2 Data Segment Registers (DSR0-7) Figure 14-32. Identier Register 3 Standard Mapping 14.3.3.3 Data Length Register (DLR) This register keeps the data length eld of the CAN frame. 14.3.3.4 Transmit Buffer Priority Register (TBPR) Table 14-34. Data Length Codes 14.3.3.5 Time Stamp Register (TSRHTSRL) 14.4 Functional Description 14.4.1 General 14.4.2 Message Storage CPU bus Transmitter MSCAN Receiver 14.4.2.1 Message Transmit Background 14.4.2.2 Transmit Structures 14.4.2.3 Receive Structures 14.4.3 Identier Acceptance Filter Page Figure 14-40. 16-bit Maskable Identier Acceptance Filters Figure 14-41. 8-bit Maskable Identier Acceptance Filters 14.4.3.1 Protocol Violation Protection 14.4.3.2 Clock System MSCAN Page 14.4.4 Timer Link 14.4.5 Modes of Operation 14.4.5.1 Normal Modes 14.4.5.2 Special Modes 14.4.5.3 Emulation Modes 14.4.5.4 Listen-Only Mode 14.4.6.1 Operation in Run Mode 14.4.6.2 Operation in Wait Mode 14.4.6.3 Operation in Stop Mode 14.4.6.4 MSCAN Sleep Mode Page Page 14.4.6.5 MSCAN Initialization Mode 14.4.6.6 MSCAN Power Down Mode 14.4.6.7 Programmable Wake-Up Function 14.4.7 Reset Initialization 14.4.8 Interrupts 14.4.8.1 Description of Interrupt Operation 14.4.8.2 Transmit Interrupt 14.4.8.3 Receive Interrupt 14.4.8.4 Wake-Up Interrupt 14.4.8.5 Error Interrupt 14.5 Initialization/Application Information 14.5.1 MSCAN initialization 14.5.2 Bus-Off Recovery Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5) 15.1 Introduction 15.1.1 Features 15.1.2 Modes of Operation 15.1.3 Block Diagram 15.2 External Signal Description 15.2.1 TXD Transmit Pin 15.2.2 RXD Receive Pin 15.3 Memory Map and Register Denition 15.3.1 Module Memory Map and Register Denition 15.3.2 Register Descriptions Figure 15-2. MC9S12XDP512 Register Summary 15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Figure 15-3. SCI Baud Rate Register (SCIBDH) Figure 15-4. SCI Baud Rate Register (SCIBDL) Table 15-2. SCIBDH and SCIBDL Field Descriptions 15.3.2.2 SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. This register is only visible in the memory map if AMAP = 0 (reset condition). Table 15-3. IRSCI Transmit Pulse Width Figure 15-5. SCI Control Register 1 (SCICR1) Table 15-5. Loop Functions Table 15-4. SCICR1 Field Descriptions (continued) 15.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Figure 15-6. SCI Alternative Status Register 1 (SCIASR1) Table 15-6. SCIASR1 Field Descriptions 15.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Figure 15-7. SCI Alternative Control Register 1 (SCIACR1) Table 15-7. SCIACR1 Field Descriptions 15.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Figure 15-8. SCI Alternative Control Register 2 (SCIACR2) Table 15-8. SCIACR2 Field Descriptions Table 15-9. Bit Error Mode Coding 15.3.2.6 SCI Control Register 2 (SCICR2) Figure 15-9. SCI Control Register 2 (SCICR2) Table 15-10. SCICR2 Field Descriptions 15.3.2.7 SCI Status Register 1 (SCISR1) Figure 15-10. SCI Status Register 1 (SCISR1) Table 15-11. SCISR1 Field Descriptions Table 15-11. SCISR1 Field Descriptions (continued) 15.3.2.8 SCI Status Register 2 (SCISR2) Figure 15-11. SCI Status Register 2 (SCISR2) Table 15-12. SCISR2 Field Descriptions 15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) 15.4 Functional Description Figure 15-14. Detailed SCI Block Diagram 15.4.1 Infrared Interface Submodule 15.4.1.1 Infrared Transmit Encoder 15.4.1.2 Infrared Receive Decoder 15.4.2 LIN Support 15.4.3 Data Format Figure 15-15. SCI Data Formats Table 15-14. Example of 8-Bit Data Formats Table 15-15. Example of 9-Bit Data Formats 15.4.4 Baud Rate Generation 15.4.5 Transmitter Figure 15-16. Transmitter Block Diagram 15.4.5.1 Transmitter Character Length 15.4.5.2 Character Transmission Page 15.4.5.3 Break Characters 15.4.5.4 Idle Characters 15.4.5.5 LIN Transmit Collision Detection 15.4.6 Receiver Figure 15-20. SCI Receiver Block Diagram 15.4.6.1 Receiver Character Length 15.4.6.2 Character Reception 15.4.6.3 Data Sampling Page Figure 15-22. Start Bit Search Example 1 Figure 15-23. Start Bit Search Example 2 Figure 15-24. Start Bit Search Example 3 Figure 15-25. Start Bit Search Example 4 Figure 15-26. Start Bit Search Example 5 Figure 15-27. Start Bit Search Example 6 15.4.6.4 Framing Errors 15.4.6.5 Baud Rate Tolerance 15.4.6.6 Receiver Wakeup 15.4.7 Single-Wire Operation 15.4.8 Loop Operation 15.5 Initialization/Application Information 15.5.1 Reset Initialization 15.5.2 Modes of Operation 15.5.2.1 Run Mode 15.5.2.2 Wait Mode 15.5.3 Interrupt Operation 15.5.3.1 Description of Interrupt Operation 15.5.4 Recovery from Wait Mode 15.5.5 Recovery from Stop Mode Page Chapter 16 Serial Peripheral Interface (S12SPIV4) 16.1 Introduction 16.1.1 Features 16.1.2 Modes of Operation 16.1.3 Block Diagram Figure 16-1. SPI Block Diagram 16.2 External Signal Description 16.2.1 MOSI Master Out/Slave In Pin 16.2.2 MISO Master In/Slave Out Pin 16.2.3 SS Slave Select Pin 16.2.4 SCK Serial Clock Pin 16.3.2 Register Descriptions Figure 16-2. SPI Register Summary 16.3.2.1 SPI Control Register 1 (SPICR1) Figure 16-3. SPI Control Register 1 (SPICR1) Table 16-2. SPICR1 Field Descriptions 16.3.2.2 SPI Control Register 2 (SPICR2) Table 16-3. SS Input / Output Selection Figure 16-4. SPI Control Register 2 (SPICR2) Table 16-4. SPICR2 Field Descriptions 16.3.2.3 SPI Baud Rate Register (SPIBR) The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) 2(SPR + 1) Eqn. 16-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 16-2 Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) 16.3.2.4 SPI Status Register (SPISR) Write: Has no effect Figure 16-6. SPI Status Register (SPISR) Table 16-8. SPISR Field Descriptions 16.3.2.5 SPI Data Register (SPIDR) Figure 16-8. Reception with SPIF Serviced in Time Figure 16-9. Reception with SPIF Serviced too Late 16.4 Functional Description 16.4.1 Master Mode 16.4.2 Slave Mode 16.4.3 Transmission Formats 16.4.3.1 Clock Phase and Polarity Controls 16.4.3.2 CPHA = 0 Transfer Format Figure 16-11. SPI Clock Format 0 (CPHA = 0) 16.4.3.3 CPHA = 1 Transfer Format Figure 16-12. SPI Clock Format 1 (CPHA = 1) 16.4.4 SPI Baud Rate Generation 16.4.5 Special Features 16.4.5.1 SS Output 16.4.5.2 Bidirectional Mode (MOMI or SISO) 16.4.6 Error Conditions 16.4.6.1 Mode Fault Error 16.4.7 Low Power Mode Options 16.4.7.1 SPI in Run Mode 16.4.7.2 SPI in Wait Mode 16.4.7.3 SPI in Stop Mode 16.4.7.4 Reset 16.4.7.5 Interrupts Chapter 17 Voltage Regulator (S12VREG3V3V5) 17.1 Introduction 17.1.1 Features 17.1.2 Modes of Operation 17.1.3 Block Diagram Figure 17-1. VREG_3V3 Block Diagram 17.2 External Signal Description 17.2.1 VDDR Regulator Power Input Pins 17.2.2 VDDA, VSSA Regulator Reference Supply Pins 17.2.3 VDD, VSS Regulator Output1 (Core Logic) Pins 17.2.4 VDDPLL, VSSPLL Regulator Output2 (PLL) Pins 17.3 Memory Map and Register Denition 17.3.1 Module Memory Map 17.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their individual bits. The VREGCTRL register allows the conguration of the VREG_3V3 low-voltage detect features. 17.3.2.1 HT Control Register (VREGHTCL) The VREGHTCL is reserved for test purposes. This register should not be written. 17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL) 17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR) The VREGAPITR register allows to trim the API timeout period. Table 17-6. Trimming Effect of APIT 17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) Figure 17-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH) Table 17-8. Selectable Autonomous Periodical Interrupt Periods 17.3.2.6 Reserved_06 17.3.2.7 Reserved_07 17.4 Functional Description 17.4.1 General 17.4.2 Regulator Core (REG) 17.4.2.1 Full Performance Mode 17.4.2.2 Reduced Power Mode 17.4.3 Low-Voltage Detect (LVD) 17.4.4 Power-On Reset (POR) 17.4.5 Low-Voltage Reset (LVR) 17.4.6 Regulator Control (CTRL) 17.4.7 Autonomous Periodical Interrupt (API) 17.4.8 Resets 17.4.9 Description of Reset Operation 17.4.9.1 Power-On Reset (POR) 17.4.9.2 Low-Voltage Reset (LVR) 17.4.10 Interrupts 17.4.10.1 Low-Voltage Interrupt (LVI) 17.4.10.2 Autonomous Periodical Interrupt (API) Page Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1) 18.1 Introduction 18.1.1 Features 18.1.2 Modes of Operation 18.1.3 Block Diagram 18.2 External Signal Description 18.3 Memory Map and Register Denition This section provides a detailed description of address space and registers used by the PIT. 18.3.1 Module Memory Map Table 18-1. MC9S12XDP512 Memory Map 18.3.2 Register Descriptions Figure 18-2. PIT Register Summary (Sheet 1 of 2) Figure 18-2. PIT Register Summary (Sheet 2 of 2) 18.3.2.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) 18.3.2.2 PIT Force Load Timer Register (PITFLT) 18.3.2.3 PIT Channel Enable Register (PITCE) Figure 18-4. PIT Force Load Timer Register (PITFLT) Table 18-3. PITFLT Field Descriptions Figure 18-5. PIT Channel Enable Register (PITCE) Table 18-4. PITCE Field Descriptions 18.3.2.4 PIT Multiplex Register (PITMUX) 18.3.2.5 PIT Interrupt Enable Register (PITINTE) Figure 18-6. PIT Multiplex Register (PITMUX) Table 18-5. PITMUX Field Descriptions Figure 18-7. PIT Interrupt Enable Register (PITINTE) Table 18-6. PITINTE Field Descriptions 18.3.2.6 PIT Time-Out Flag Register (PITTF) Write: Anytime (write to clear); writes to the reserved bits have no effect Figure 18-10. PIT Micro Timer Load Register 1 (PITMTLD1) 18.3.2.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD01) Figure 18-8. PIT Time-Out Flag Register (PITTF) Table 18-7. PITTF Field Descriptions Table 18-8. PITMTLD01 Field Descriptions 18.3.2.8 PIT Load Register 0 to 3 (PITLD03) Figure 18-11. PIT Load Register 0 (PITLD0) Figure 18-12. PIT Load Register 1 (PITLD1) Figure 18-13. PIT Load Register 2 (PITLD2) Figure 18-14. PIT Load Register 3 (PITLD3) Table 18-9. PITLD03 Field Descriptions 18.3.2.9 PIT Count Register 0 to 3 (PITCNT03) Figure 18-15. PIT Count Register 0 (PITCNT0) Figure 18-16. PIT Count Register 1 (PITCNT1) Figure 18-17. PIT Count Register 2 (PITCNT2) Figure 18-18. PIT Count Register 3 (PITCNT3) Table 18-10. PITCNT03 Field Descriptions 18.4 Functional Description 18.4.1 Timer 18.4.2 Interrupt Interface 18.4.3 Hardware Trigger 18.5 Initialization/Application Information 18.5.1 Startup 18.5.2 Shutdown 18.5.3 Flag Clearing Page Chapter 19 Background Debug Module (S12XBDMV2) 19.1 Introduction 19.1.1 Features 19.1.2 Modes of Operation 19.1.2.1 Regular Run Modes 19.1.2.2 Secure Mode Operation 19.1.2.3 Low-Power Modes 19.1.3 Block Diagram 19.2 External Signal Description 19.3 Memory Map and Register Denition 19.3.1 Module Memory Map 19.3.2 Register Descriptions Figure 19-2. BDM Register Summary 19.3.2.1 BDM Status Register (BDMSTS) Table 19-2. BDMSTS Field Descriptions (continued) 19.3.2.2 BDM CCR LOW Holding Register (BDMCCRL) 19.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH) 19.3.2.4 BDM Global Page Index Register (BDMGPR) 19.3.3 Family ID Assignment 19.4 Functional Description 19.4.1 Security 19.4.2 Enabling and Activating BDM 19.4.3 BDM Hardware Commands 19.4.4 Standard BDM Firmware Commands Table 19-5. Hardware Commands Table 19-6. Firmware Commands 19.4.5 BDM Command Structure Page 19.4.6 BDM Serial Interface Figure 19-8. BDM Host-to-Target Serial Bit Timing Figure 19-9. BDM Target-to-Host Serial Bit Timing (Logic 1) 19.4.7 Serial Interface Hardware Handshake Protocol Page 19.4.8 Hardware Handshake Abort Procedure Page Page 19.4.9 SYNC Request Timed Reference Pulse 19.4.10 Instruction Tracing 19.4.11 Serial Communication Time Out Page Chapter 20 Debug (S12XDBGV2) 20.1 Introduction 20.1.1 Glossary of Terms 20.1.2 Features 20.1.3 Modes of Operation 20.1.4 Block Diagram Figure 20-1 shows a block diagram of the debug module. Figure 20-1. Debug Block Diagram 20.2 External Signal Description Table 20-1. Mode Dependent Restriction Summary Page 20.3 Memory Map and Register Denition Figure 20-2. DBG Register Summary 20.3.1 Register Descriptions 20.3.1.1 Debug Control Register 1 (DBGC1) Table 20-3. DBGC1 Field Descriptions Table 20-4. DBGBRK Encoding Table 20-5. COMRV Encoding 20.3.1.2 Debug Status Register (DBGSR) Write: Never Figure 20-4. Debug Status Register (DBGSR) Table 20-6. DBGSR Field Descriptions Table 20-7. SSF[2:0] State Sequence Flag Bit Encoding Table 20-5. COMRV Encoding 20.3.1.3 Debug Trace Control Register (DBGTCR) Write: Bits 7:6 only when DBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Figure 20-5. Debug Trace Control Register (DBGTCR) Table 20-8. DBGTCR Field Descriptions Table 20-9. TSOURCE Trace Source Bit Encoding Table 20-10. TRANGE Trace Range Encoding 20.3.1.4 Debug Control Register2 (DBGC2) Write: Anytime the module is disarmed. This register congures the comparators for range matching. Table 20-11. TRCMOD Trace Mode Bit Encoding Table 20-12. TALIGN Trace Alignment Encoding Figure 20-6. Debug Control Register2 (DBGC2) 20.3.1.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Table 20-14. CDCM Encoding Table 20-15. ABCM Encoding Figure 20-7. Debug Trace Buffer Register (DBGTBH) Figure 20-8. Debug Trace Buffer Register (DBGTBL) Table 20-16. DBGTB Field Descriptions 20.3.1.6 Debug Count Register (DBGCNT) Write: Never Figure 20-9. Debug Count Register (DBGCNT) Table 20-17. DBGCNT Field Descriptions Table 20-18. CNT Decoding Table 20.3.1.7 Debug State Control Registers 20.3.1.8 Debug State Control Register 1 (DBGSCR1) 20.3.1.9 Debug State Control Register 2 (DBGSCR2) 20.3.1.10 Debug State Control Register 3 (DBGSCR3) Table 20-22. DBGSCR2 Field Descriptions Figure 20-12. Debug State Control Register 3 (DBGSCR3) Table 20-23. State2 Sequencer Next State Selection 20.3.1.11 Comparator Register Descriptions Table 20-26. Comparator Register Layout Figure 20-13. Debug Comparator Control Register (Comparators A and C) Table 20-28. Read or Write Comparison Logic Table Table 20-27. DBGXCTL Field Descriptions (continued) 20.3.1.11.2 Debug Comparator Address High Register (DBGXAH) 20.3.1.11.3 Debug Comparator Address Mid Register (DBGXAM) Figure 20-15. Debug Comparator Address High Register (DBGXAH) Table 20-29. DBGXAH Field Descriptions Figure 20-16. Debug Comparator Address Mid Register (DBGXAM) Table 20-30. DBGXAM Field Descriptions 20.3.1.11.4 Debug Comparator Address Low Register (DBGXAL) 20.3.1.11.5 Debug Comparator Data High Register (DBGXDH) Figure 20-17. Debug Comparator Address Low Register (DBGXAL) Table 20-31. DBGXAL Field Descriptions Figure 20-18. Debug Comparator Data High Register (DBGXDH) Table 20-32. DBGXDH Field Descriptions 20.3.1.11.6 Debug Comparator Data Low Register (DBGXDL) 20.3.1.11.7 Debug Comparator Data High Mask Register (DBGXDHM) Figure 20-19. Debug Comparator Data Low Register (DBGXDL) Table 20-33. DBGXDL Field Descriptions 20.4 Functional Description 20.4.1 DBG Operation 20.4.2 Comparator Modes 20.4.2.1 Exact Address Comparator Match (Comparators A and C) 20.4.2.2 Exact Address Comparator Match (Comparators B and D) 20.4.2.3 Range Comparisons 20.4.3 Trigger Modes 20.4.3.1 Trigger On Comparator Match 20.4.3.2 Trigger On Comparator Related Taghit 20.4.3.3 External Tag Trigger 20.4.3.4 Trigger On XGATE S/W Breakpoint Request 20.4.3.5 Immediate Trigger 20.4.3.6 Trigger Priorities 20.4.4 State Sequence Control 20.4.4.1 Final State 20.4.5 Trace Buffer Operation 20.4.5.1 Trace Trigger Alignment 20.4.5.2 Trace Modes 20.4.5.3 Trace Buffer Organization Page Figure 20-24. XGATE Information Byte XINF Table 20-40. XINF Field Descriptions Figure 20-25. CPU Information Byte CINF Table 20-41. CINF Field Descriptions Page Page 20.4.6 Tagging 20.4.6.1 External Tagging using TAGHI and TAGLO 20.4.7 Breakpoints 20.4.7.1 XGATE Software Breakpoints 20.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers 20.4.7.3 Breakpoints Generated Via The TRIG Bit 20.4.7.4 Breakpoints via TAGHI Or TAGLO Pin Taghits 20.4.7.5 DBG Breakpoint Priorities Page Page Page Page Page Page Page Page Page Page Page Page Page Chapter 21 Interrupt (S12MC9S12XDP512V1) 21.1 Introduction 21.1.1 Glossary 21.1.2 Features 21.1.3 Modes of Operation Page 21.1.4 Block Diagram Figure 21-1 shows a block diagram of the XINT module. Figure 21-1. XINT Block Diagram Page 21.3.1 Register Descriptions This section describes in address order all the XINT registers and their individual bits. Figure 21-2. XINT Register Summary 21.3.1.1 Interrupt Vector Base Register (IVBR) Figure 21-3. Interrupt Vector Base Register (IVBR) Table 21-2. IVBR Field Descriptions 21.3.1.2 XGATE Interrupt Priority Conguration Register (INT_XGPRIO) Table 21-4. XGATE Interrupt Priority Levels 21.3.1.3 Interrupt Request Conguration Address Register (INT_CFADDR) Figure 21-5. Interrupt Conguration Address Register (INT_CFADDR) Table 21-5. INT_CFADDR Field Descriptions 21.3.1.4 Interrupt Request Conguration Data Registers (INT_CFDATA07) Figure 21-9. Interrupt Request Conguration Data Register 3 (INT_CFDATA3) Figure 21-6. Interrupt Request Conguration Data Register 0 (INT_CFDATA0) Figure 21-7. Interrupt Request Conguration Data Register 1 (INT_CFDATA1) Figure 21-8. Interrupt Request Conguration Data Register 2 (INT_CFDATA2) Figure 21-10. Interrupt Request Conguration Data Register 4 (INT_CFDATA4) Figure 21-11. Interrupt Request Conguration Data Register 5 (INT_CFDATA5) Figure 21-13. Interrupt Request Conguration Data Register 7 (INT_CFDATA7) Figure 21-12. Interrupt Request Conguration Data Register 6 (INT_CFDATA6) Table 21-6. INT_CFDATA07 Field Descriptions Table 21-7. Interrupt Priority Levels 21.4 Functional Description 21.4.1 S12X Exception Requests 21.4.2 Interrupt Prioritization 21.4.2.1 Interrupt Priority Stack 21.4.3 XGATE Requests 21.4.3.1 XGATE Request Prioritization 21.4.4 Priority Decoders 21.4.5 Reset Exception Requests 21.4.6 Exception Priority 21.5 Initialization/Application Information 21.5.1 Initialization 21.5.2 Interrupt Nesting 21.5.3 Wake Up from Stop or Wait Mode 21.5.3.1 CPU Wake Up from Stop or Wait Mode 21.5.3.2 XGATE Wake Up from Stop or Wait Mode Page Chapter 22 External Bus Interface (S12XEBIV2) 22.1 Introduction 22.1.1 Features 22.1.2 Modes of Operation 22.1.3 Block Diagram 22.2 External Signal Description Table 22-1. External System Signals Associated with MC9S12XDP512 22.3 Memory Map and Register Denition 22.3.1 Module Memory Map 22.3.2 Register Descriptions 22.3.2.1 External Bus Interface Control Register 0 (EBICTL0) Table 22-3. Input Threshold Levels on External Signals Table 22-4. External Address Bus Size 22.3.2.2 External Bus Interface Control Register 1 (EBICTL1) This register is used to configure the external access stretch (wait) function. Figure 22-4. External Bus Interface Control Register 1 (EBICTL1) Table 22-5. EBICTL1 Field Descriptions Table 22-6. External Access Stretch Bit Denition 22.4 Functional Description 22.4.1 Operating Modes and External Bus Properties A summary of the external bus interface functions for each operating mode is shown in Table 22-7. Table 22-7. Summary of Functions 22.4.2 Internal Visibility 22.4.2.1 Access Source and Instruction Queue Status Signals 22.4.2.2 Emulation Modes Timing Table 22-9. Read Access (1 Cycle) Table 22-10. Read Access (2 Cycles) Table 22-11. Read Access (n1 Cycles) 22.4.2.2.2 Write Access Timing Table 22-12. Write Access (1 Cycle) Access #0 Access #1 Access #2 Table 22-13. Write Access (2 Cycles) Table 22-14. Write Access (n1 Cycles) 22.4.2.3 Internal Visibility Data 22.4.3 Accesses to Port Replacement Registers 22.4.4 Stretched External Bus Accesses 22.4.5 Data Select and Data Direction Signals 22.4.5.1 Normal Expanded Mode 22.4.5.2 Emulation Modes and Special Test Mode Table 22-17. Access in Normal Expanded Mode Table 22-18. Access in Emulation Modes and Special Test Mode 22.4.6 Low-Power Options 22.4.6.1 Run Mode 22.5 Initialization/Application Information 22.5.1 Normal Expanded Mode 22.5.1.1 Example 1a: External Wait Feature Disabled 22.5.1.2 Example 1b: External Wait Feature Enabled 22.5.2 Emulation Modes 22.5.2.1 Example 2a: Emulation Single-Chip Mode 22.5.2.2 Example 2b: Emulation Expanded Mode Page Chapter 23 Memory Mapping Control (S12XMMCV2) 23.1 Introduction 23.1.1 Features 23.1.2 Modes of Operation 23.1.2.1 Power Saving Modes 23.2 External Signal Description Table 23-1. External Input Signals Associated with the MMC Table 23-2. External Output Signals Associated with the MMC 23.3 Memory Map and Registers 23.3.1 Module Memory Map Figure 23-2. MMC Register Summary 23.3.2 Register Descriptions Figure 23-2. MMC Register Summary 23.3.2.1 MMC Control Register (MMCCTL0) Figure 23-3. MMC Control Register (MMCCTL0) Table 23-3. Chip Selects Function Activity The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects. Table 23-4. MMCCTL0 Field Descriptions Table 23-5. Chip Select Signals 23.3.2.2 Mode Register (MODE) Figure 23-5. Mode Transition Diagram when MCU is Unsecured 23.3.2.3 Global Page Index Register (GPAGE) 23.3.2.4 Direct Page Register (DIRECT) 23.3.2.5 MMC Control Register (MMCCTL1) 23.3.2.6 RAM Page Index Register (RPAGE) Page 23.3.2.7 EEPROM Page Index Register (EPAGE) 23.3.2.8 Program Page Index Register (PPAGE) 23.3.2.9 RAM Write Protection Control Register (RAMWPC) Table 23-13. PPAGE Field Descriptions Figure 23-17. RAM Write Protection Control Register (RAMWPC) Table 23-14. RAMWPC Field Descriptions 23.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU) Write: Anytime when RWPE = 0 23.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL) Figure 23-18. RAM XGATE Upper Boundary Register (RAMXGU) Table 23-15. RAMXGU Field Descriptions 23.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU) 23.4 Functional Description 23.4.1 MCU Operating Mode 23.4.2 Memory Map Scheme 23.4.2.1 CPU and BDM Memory Map Scheme Figure 23-21. Expansion of the Local Address Map CPU or BDM Page 23.4.2.2 Global Addresses Based on the Global Page Figure 23-22. BDMGPR Address Mapping 23.4.2.3 Implemented Memory Map Table 23-19. Global Implemented Memory Space Page Figure 23-23. Local to Implemented Global Address Mapping (Without GPAGE) CPU and BDM 23.4.2.4 XGATE Memory Map Scheme Figure 23-24. Local to Global Address Mapping (XGATE) XGATE 23.4.3 Chip Access Restrictions 23.4.3.1 Illegal XGATE Accesses 23.4.3.2 Illegal CPU Accesses Figure 23-25. RAM Write Protection Scheme Table 23-22. RAM Write Protection Interrupt Vectors 23.4.4 Chip Bus Control 23.4.4.1 Master Bus Prioritization 23.4.4.2 Access Conicts on Target Buses 23.4.5 Interrupts 23.4.5.1 Outgoing Interrupt Requests 23.5 Initialization/Application Information 23.5.1 CALL and RTC Instructions 23.5.2 Port Replacement Registers (PRRs) Page 23.5.3 On-Chip ROM Control 23.5.3.1 ROM Control in Single-Chip Modes 23.5.3.2 ROM Control in Emulation Single-Chip Mode 23.5.3.3 ROM Control in Normal Expanded Mode 23.5.3.4 ROM Control in Emulation Expanded Mode Figure 23-31. ROMON = 0 in Emulation Expanded Mode 23.5.3.5 ROM Control in Special Test Mode Figure 23-32. ROM in Special Test Mode Page Appendix A Electrical Characteristics A.1 General A.1.1 Parameter Classication A.1.2 Power Supply A.1.3 Pins A.1.3.1 I/O Pins A.1.3.2 Analog Reference A.1.3.3 Oscillator A.1.3.4 TEST A.1.5 Absolute Maximum Ratings T able A-1. Absolute Maxim um Ratings A.1.6 ESD Protection and Latch-up Immunity Table A-2. ESD and Latch-up Test Conditions Table A-3. ESD and Latch-Up Protection Characteristics A.1.7 Operating Conditions Table A-4. Operating Conditions A.1.8 Power Dissipation and Thermal Characteristics T able A-5. Thermal P ackage Characteristics A.1.9 I/O Characteristics Table A-6. 3.3-V I/O Characteristics Table A-7. 5-V I/O Characteristics A.1.10 Supply Currents A.1.10.1 Measurement Conditions Table A-9. shows the conguration of the peripherals for run current measurement. Table A-9. Peripheral Congurations for Run Supply Current Measurements A.1.10.2 Additional Remarks Table A-10. Run and Wait Current Characteristics Table A-11. Pseudo Stop and Full Stop Current A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics Table A-12. ATD 5-V Operating Characteristics Table A-13. ATD Operating Characteristics 3.3V A.2.2 Factors Inuencing Accuracy A.2.2.1 Source Resistance A.2.2.2 Source Capacitance A.2.2.3 Current Injection A.2.3 ATD Accuracy A.2.3.1 5-V Range A.2.3.2 3.3-V Range Table A-15. 5-V ATD Conversion Performance Table A-16. 3.3-V ATD Conversion Performance Figure A-1 shows only denitions, for specication values refer to Table A-15. A.3 NVM, Flash, and EEPROM A.3.1 NVM Timing A.3.1.1 Single Word Programming A.3.1.2 Burst Programming A.3.1.3 Sector Erase A.3.1.4 Mass Erase A.3.1.5 Blank Check Table A-17. NVM Timing Characteristics A.3.2 NVM Reliability T able A-18. NVM Reliability Characteristics Typical Endurance [103Cycles] Operating Temperature TJ [C] A.4 Voltage Regulator Table A-19. Voltage Regulator Electrical Characteristics A.5 Reset, Oscillator, and PLL A.5.1 Startup A.5.1.1 POR A.5.1.2 SRAM Data Retention A.5.1.3 External Reset A.5.2 Oscillator Table A-21. Oscillator Characteristics A.5.3 Phase Locked Loop A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good lter characteristics. A.5.3.2 Jitter Information Page A.6 MSCAN A.7 SPI Timing Table A-22. PLL Characteristics Table A-23. MSCAN Wake-up Pulse Characteristics Table A-24. Measurement Conditions A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted. Figure A-7. SPI Master Timing (CPHA = 1) Figure A-6. SPI Master Timing (CPHA = 0) In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted. A.7.2 Slave Mode Figure A-8. SPI Slave Timing (CPHA = 0) In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. Table A-25. SPI Master Mode Timing Characteristics In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. Figure A-9. SPI Slave Timing (CPHA = 1) In Table A-26 the timing characteristics for slave mode are listed. Table A-26. SPI Slave Mode Timing Characteristics A.8 External Bus Timing Figure A-10. Example 1a: Normal Expanded Mode Read Followed by Write A.8.1 Normal Expanded Mode (External Wait Feature Disabled) Table A-27. Example 1a: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 0) A.8.2 Normal Expanded Mode (External Wait Feature Enabled) Figure A-11. Example 1b: Normal Expanded Mode Stretched Read Access Figure A-12. Example 1b: Normal Expanded Mode Stretched Write Access Table A-28. Example 1b: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 1) A.8.3 Emulation Single-Chip Mode (Without Wait States) Figure A-13. Example 2a: Emulation Single-Chip Mode Read Followed by Write T able A-29. Example 2a: Emulation Single-Chip Mode Timing V A.8.4 Emulation Expanded Mode (With Optional Access Stretching) Figure A-14. Example 2b: Emulation Expanded Mode Read with 1 Stretch Cycle Figure A-15. Example 2b: Emulation Expanded Mode Write with 1 Stretch Cycle T able A-30. Example 2b: Emulation Expanded Mode Timing V A.8.5 External Tag Trigger Timing Figure A-16. External Trigger Timing Table A-31. External Tag Trigger Timing VDD35 = 5.0 V Page B.2 144-Pin LQFP Figure B-1. 144-Pin LQFP Mechanical Dimensions (Case No. 918-03) B.3 112-Pin LQFP Package Figure B-2. 112-Pin LQFP Mechanical Dimensions (Case No. 987) B.4 80-Pin QFP Package Figure B-3. 80-Pin QFP Mechanical Dimensions (Case No. 841B) Appendix C Recommended PCB Layout Table C-1. Recommended Decoupling Capacitor Choice Figure C-1. 144-Pin LQFP Recommended PCB Layout Figure C-2. 112-Pin LQFP Recommended PCB Layout Figure C-3. 80-Pin QFP Recommended PCB Layout Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XD - Family Page D.2 Memory Sizes and Package Options S12XA - Family D .3 MC9S12XD-F amily Flash Conguration D.4 Peripheral Sets S12XD - Family D.5 Peripheral Sets S12XA - Family D.6 Pinout explanations: Appendix E Ordering Information MC9S12X DP512 C FU Page Page Table E-1. MC and SC Part Numbers Page How to Reach Us: Home Page: www.freescale.com