Freescale Semiconductor MC9S12XDP512 Chapter 5 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 271
Chapter 5
Clocks and Reset Generator (S12CRGV6)
5.1 Introduction
This specification describes the function of the clocks and reset generator (MC9S12XDP512).
5.1.1 Features
The main features of this block are:
• Phase locked loop (PLL) frequency multiplier
— Reference divider
— Automatic bandwidth control mode for low-jitter operation
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self clock mode in absence of reference clock
• System clock generator
— Clock quality check
— User selectable fast wake-up from Stop in self-clock mode for power saving and immediate
program execution
— Clock switch for either oscillator or PLL based system clocks
• Computer operating properly (COP) watchdog timer with time-out clear window
• System reset generation from the following possible sources:
— Power on reset
— Low voltage reset
— Illegal address reset
— COP reset
— Loss of clock reset
— External pin reset
• Real-time interrupt (RTI)