Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 551
Figure 11-67. Detailed Timer Block Diagram in Queue Mode when PRNT = 0
16 BIT MAIN TIMER
P1
TC0H Hold Reg.
P0
P3
P2
P4
P5
P6
P7
EDG0
EDG1
EDG2
EDG3
MUX
Bus Clock
16-Bit Load Register
16-Bit Modulus
0RESET
EDG0
EDG1
EDG2
EDG4
EDG5
EDG3
EDG6
EDG7
÷1, 2, ..., 128
÷ 1, 4, 8, 16
LATCH0
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Bus Clock
TC1H Hold Reg.
TC2H Hold Reg.
TC3H Hold Reg.
MUX
MUX
MUX
PA0H Hold Reg.
PAC0
0RESET
PA1H Hold Reg.
PAC1
0RESET
PA2H Hold Reg.
PAC2
0RESET
PA3H Hold Reg.
PAC3
LATCH1
LATCH3
LATCH2
LATQ, BUFEN
(Queue Mode)
Read TC3H
Hold Reg.
Read TC2H
Hold Reg.
Read TC1H
Hold Reg.
Read TC0H
Hold Reg.
Down Counter
SH04
SH15
SH26
SH37
Timer
Prescaler
16-Bit Free-Running
Main Timer
Delay
Counter
Delay
Counter
Delay
Counter
Delay
Counter
Modulus
Prescaler
Comparator
TC0 Capture/Compare Reg.
Comparator
TC1 Capture/Compare Reg.
Comparator
TC2 Capture/Compare Reg.
Comparator
TC3 Capture/Compare Reg.
Comparator
TC4 Capture/Compare Reg.
Comparator
TC5 Capture/Compare Reg.
Comparator
TC6 Capture/Compare Reg.
Comparator
TC7 Capture/Compare Reg.