Freescale Semiconductor MC9S12XDP512 Figure 5-25. RESET Timing, Table 5-15. Reset Vector Selection, ) ( ) (

Chapter 5 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.11
306 Freescale Semiconductor
NOTE
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
Figure 5-25. RESET Timing
Table 5-15. Reset Vector Selection
Sampled RESET Pin
(64 cycles
after release)
Clock Monitor
Reset Pending
COP
Reset Pending Vector Fetch
1 0 0 POR / LVR / Illegal Address Reset / External Reset
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR / LVR / Illegal Address Reset / External Reset
with rise of RESET pin
) ( ) (
)
(
)
SYSCLK
128 + n cycles 64 cycles
With nbeing
min 3 / max 6
cycles depending
on internal
synchronization
delay
CRG drives RESET pin low
Possibly
SYSCLK
not
running
Possibly
RESET
driven low
externally
)
(
(
RESET
RESET pin
released