Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 421
Operation
!RS1[w:0] RD[w+o:o];
w= (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD at
position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0
as a RS1, this command can be used to set bits.
CCR Effects
Code and CPU Cycles
BFINSI Bit Field Insert and Invert BFINSI
NZVC
∆∆0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: 0; cleared.
C: Not affected.
Source Form Address
Mode Machine Code Cycles
BFINSI RD, RS1, RS2 TRI 0 1 1 1 0 RD RS1 RS2 1 1 P
W4 O4
15 025
W4=3, O4=2
15 03
Inverted Bit Field Insert
RS2
RD
RS1
15 0374