Freescale Semiconductor MC9S12XDP512 A.7.2 Slave Mode

Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.11
952 Freescale Semiconductor
In Table A-25 the timing characteristics for master mode are listed.
A.7.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
Figure A-8. SPI Slave Timing (CPHA = 0)
Table A-25. SPI Master Mode Timing Characteristics
Num C Characteristic Symbol Min Typ Max Unit
1 D SCK frequency fsck 1/2048 — 1/2f
bus
1 D SCK period tsck 2 — 2048 tbus
2 D Enable lead time tlead — 1/2 — tsck
3 D Enable lag time tlag — 1/2 — tsck
4 D Clock (SCK) high or low time twsck — 1/2 — tsck
5 D Data setup time (inputs) tsu 8——ns
6 D Data hold time (inputs) thi 8——ns
9 D Data valid after SCK edge tvsck — — 29 ns
10 D Data valid after SS fall (CPHA = 0) tvss — — 15 ns
11 D Data hold time (outputs) tho 20 — — ns
12 D Rise and fall time inputs trfi —— 8 ns
13 D Rise and fall time outputs trfo —— 8 ns
SCK
(Input)
SCK
(Input)
MOSI
(Input)
MISO
(Output)
SS
(Input)
1
9
5 6
MSB IN
Bit 6 . . . 1
LSB IN
Slave MSB Slave LSB OUT
Bit 6 . . . 1
11
4
4
2
7
(CPOL = 0)
(CPOL = 1)
3
13
NOTE: Not defined
12
12
11
See
13
Note
8
10
See
Note