Chapter 2---System Description
J32 |
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| 1 |
| GND | ||
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FROM |
| IIC_CLK |
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2 |
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| IIC_DATA | ||||
SCB | 3 |
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| /IIC_SINT | ||||
| 4 |
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| J31 |
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| 1 |
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| GND | ||
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| 2 |
| X_RED_CONV | |||
FROM 4 |
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X_GRN_CONV | ||||||
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SCB | 6 |
| X_BLU_CONV | |||
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| 8 |
| Y_RED_CONV | |||
| 10 |
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| Y_GRN_CONV | |||||
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| 12 | Y_BLU_CONV | ||||
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| 18 |
| CORR_SYNC | |||
| 16 |
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| GND |
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FROM RTG 17 | V_DRIVE | |||||
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J33
FROM HVDB 5 WIDTH_CONTROL
J32 |
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| 5 |
| +5.1V | ||
| 6 |
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FROM |
| 6ND | |||
7 |
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| +15V | ||||
LVPS |
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9 |
| GND | |||
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11 | |||||
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| 13 | GND |
CONVERGENCE/ DEFLECTION BOARD
RED_ILA+
RED_ILA-
GRN_ILA+
GRN_ILA-
BLU_ILA+
BLU_ILA-
X_RED+
X_RED-
X_GRN+
X_GRN-
X_BLU+
X_BLU-
Y_RED+
Y_RED-
Y_GRN+
Y_GRN-
Y_BLU+
Y_BLU-
GND H_PARABOLA
V_PARABOLA
V_RAMP
V_PARAB
GND
J38
1
2TO
4ILAs
5
7
8
J39
1
2
TO/FROM 34 SRB
5
6
J40
1
2
3TO/FROM
4SRB
5
6
J31
13TO
14HVPS
15
J33
1FROM
32HVDB
Figure 2-15. Convergence/Deflection Board I/O diagram.
IIC interface
Adjustments for this board are performed by the System Controller via the IIC serial bus interface. This three wire bus interface consists of a clock line, a data line and an interrupt line. The C/D Board does not create any IIC interrupt. The following table lists all adjustments performed via the IIC bus interface (I = Input to C/D Board, O = Output from C/D Board):
Table | Convergence/Deflection IIC communication | |||
Input/ | No. of |
| Information | Description |
Output | bits |
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I | 1 |
| ILA_FREQ_N1 | Data for selection of frequency of ILA bias circuit |
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I | 1 |
| ILA_FREQ_N2 | Data for selection of frequency of ILA bias circuit |
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I | 1 |
| ILA_FREQ_N3 | Data for selection of frequency of ILA bias circuit |
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Model 200 Service Manual |