Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs

Connections Without Ethernet Statistics

Ethernet AVB Endpoint

Core Netlist

tx_clk tx_clk_en

tx_data[7:0] tx_data_valid tx_underrun tx_ack

rx_clk rx_clk_en

rx_data[7:0] rx_data_valid rx_frame_good rx_frame_bad

host_opcode[1:0] host_addr[9:0] host_wr_data[31:0] host_req host_miim_sel host_miim_rdy host_rd_data_mac[31:0]

host_rd_data_stats[31:0] host_stats_lsw_rdy host_stats_msw_rdy

host_clk

GND

host_clk

 

 

 

 

TEMAC Block-level Wrapper

 

 

 

 

 

(from TEMAC Example Design)

 

 

 

 

 

pause_req

 

 

 

 

 

 

pause_val[15:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

tx_clk

 

 

 

 

 

 

tx_clk_en

 

 

 

 

 

 

tx_data[7:0]

tx_statistics_valid

 

 

 

 

 

tx_data_valid

 

 

 

 

 

tx_statistics_vector[31:0]

 

 

 

 

 

tx_underrun

 

 

 

 

 

 

 

 

 

 

 

tx_ack

 

 

NC

 

tx_collision

 

 

 

 

 

NC

 

tx_retransmit

 

 

 

 

 

 

 

 

 

tx_ifg_delay[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

rx_clk

 

 

 

 

 

 

rx_clk_en

rx_statistics_valid

 

 

 

 

 

 

 

 

 

 

 

rx_data[7:0]

rx_statistics_vector[27:0]

 

 

 

 

 

 

 

 

 

 

rx_data_valid

 

 

 

 

 

 

rx_frame_good

 

 

 

 

 

 

rx_frame_bad

 

 

 

 

 

 

host_opcode[1:0]

 

 

 

 

 

 

host_addr[9:0]

 

 

 

 

 

 

host_wr_data[31:0]

 

 

 

 

 

 

host_req

 

 

 

 

 

 

host_miim_sel

 

 

 

 

 

 

host_miim_rdy

 

 

 

 

 

 

host_rd_data[31:0]

 

 

 

 

 

 

host_clk

 

 

 

 

 

 

 

 

 

NC NC

NC NC

Figure 12-1:Connection to the Tri-Mode Ethernet MAC Core (without Ethernet Statistics)

Figure 12-1illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (TEMAC) core when not using the Ethernet Statistics core.

Figure 12-1provides detail for the connections between the two cores which were shown in Figure 5-1.

All connections, as shown, are logic-less connections. Because the AVB standard does not include support for half-duplex or flow control operation, the relevant half-duplex/flow- control signals of the TEMAC can be left unused: inputs can be tied to logic 0, outputs can be left unconnected.

Ethernet AVB Endpoint User Guide

www.xilinx.com

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UG492 July 23, 2010

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Xilinx UG492 manual Connections Without Ethernet Statistics, Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs