Xilinx UG492 manual Directory and File Contents

Chapter 15: Detailed Example Design (Standard Format)

<component_name>/drivers/v2_04_a

Files for compiling the low-level drivers provided with the core

drivers/avb_v2_04_a/data

Data files for automatic integration into Xilinx Platform Studio

drivers/avb_v2_04_a/examples

An application example using the low-level driver files

drivers/avb_v2_04_a/src

Low-level driver source C files

Directory and File Contents

The core directories and their associated files are defined in the following tables.

<project directory>

The project directory contains all the CORE Generator software project files.

Table 15-1:Project Directory

Name		Description
	<project_dir>
<component_name>.ngc		Top-level netlist. This is instantiated by
		the Verilog or VHDL example design.
<component_name>.v[hd]		Verilog or VHDL simulation model;
		UniSim-based.
<component_name>.v{hoeo}		Verilog or VHDL instantiation template
		for the core.
<component_name>.xco		Log file that records the settings used to
		generate a core. An XCO file is
		generated by the CORE Generator
		software for each core that it creates in
		the current project directory. An XCO
		file can also be used as an input to the
		CORE Generator software.
<component_name>_flist.txt		List of files delivered with the core.
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144	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010