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Xilinx UG492 manual Directory and File Contents, Detailed Example Design EDK format

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Chapter 16: Detailed Example Design (EDK format)

Directory and File Contents

The core directories and their associated files are defined in the following tables.

<project directory>

The project directory contains all the CORE Generator software project files.

Table 16-1:Project Directory

Name		Description

	<project_dir>

<component_name>.ngc		Top-level netlist. This is instantiated by
		the Verilog or VHDL example design.

<component_name>.xco		Log file that records the settings used to
		generate a core. An XCO file is
		generated by the CORE Generator
		software for each core that it creates in
		the current project directory. An XCO
		file can also be used as an input to the
		CORE Generator software.

<component_name>_flist.txt		List of files delivered with the core.

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<project directory>/<component name>

The <component name> directory contains the release notes file provided with the core, which may include last-minute changes and updates.

Table 16-2:Component Name Directory

Name	Description

<project_dir>/<component_name>

eth_avb_endpoint_readme.txt	Core release notes file.

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160	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

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Xilinx UG492 manual Directory and File Contents, Detailed Example Design EDK format

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23Revision History Date Version RevisionTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home NetworkConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This GuideConventions TypographicalConventions Online DocumentConvention Meaning or Use Example List of Abbreviations Acronym Spelled OutConventions Acronym Spelled Out VhdlPreface About This Guide Introduction System RequirementsAbout the Core WindowsRecommended Design Experience Additional Core ResourcesTechnical Support FeedbackDocument FeedbackIntroduction Licensing the Core Before you Begin License OptionsSimulation Only Full System Hardware EvaluationInstalling the License File Obtaining Your License KeyOverview of Ethernet Audio Video Bridging 1Example AVB Home NetworkP802.1AS AVB SpecificationsOverview of Ethernet Audio Video Bridging AVB Specifications P802.1QavTalker Assumptions Listener AssumptionsTypical Implementation P802.1QatTypical Implementation UG492 July 23 Generating the Core Ethernet AVB GUICore Delivery Format Component NameGenerating the Core PLB Base Address Number of PLB MastersEthernet AVB GUI Parameter Values in the XCO File Output GenerationCore Architecture Standard Core Generator Format Core ArchitectureEDK pcore Format EDK pcore FormatFunctional Block Description PLB InterfaceAV Traffic Interface Legacy Traffic InterfaceTx Arbiter Rx SplitterMAC Header Filters Functional Block DescriptionPrecise Timing Protocol Blocks Tx PTP Packet BuffersTx Time Stamp Rx PTP Packet BuffersRTC Software Drivers Tri-Mode Ethernet MACsClocks and Reset 1Clocks and Resets Signal Direction DescriptionCore Interfaces Core InterfacesLegacy Traffic Receiver Path Signals Legacy Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path Direction Description 3Legacy Traffic Signals Receiver Path AV Traffic Transmitter Path Signals4AV Traffic Signals Transmitter Path Direction Description AV Traffic Receiver Path Signals 5AV Traffic Signals Receiver Path Direction DescriptionTri-Mode Ethernet MAC Client Interface MAC Transmitter InterfaceMAC Receiver Interface MAC Management InterfaceProcessor Local Bus PLB Interface PLB Interface PIN Name Direction DescriptionEthernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction DescriptionPTP Signals Signal Direction DescriptionEthernet AVB Endpoint Transmission Tx Legacy Traffic I/FError Free Legacy Frame Transmission Ethernet AVB Endpoint TransmissionTx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Tx Arbiter OverviewCredit Based Traffic Shaping Algorithm Tx Arbiter4Credit-based Shaper Operation IdleSlope Tx Arbiter Bandwidth ControlSendSlope HiLimit LoLimitRx Splitter Ethernet AVB Endpoint ReceptionRx Legacy Traffic I/F Error Free Legacy Frame Reception Ethernet AVB Endpoint ReceptionErrored Legacy Frame Reception Legacy MAC Header FiltersOverview of Operation Rx Legacy Traffic I/F3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA MatchPartial Destination Address DA Match 5Filtering of Frames with a Partial DA MatchVlan Priority Match Any Other CombinationsRx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic InterfaceReal Time Clock and Time Stamping Real Time ClockReal Time Clock and Time Stamping Increment of Nanoseconds Field RTC ImplementationReal Time Clock Controlled Frequency RTC Increment of the Seconds FieldSynchronized RTC Time Stamping Logic Time Stamping LogicTime Stamp Sampling Position of MAC Frames 3Time Stamping PositionIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet BufferPrecise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer StructureRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Processor Local Bus Interface Configuration and StatusSingle Read Transaction Configuration and Status 1Single Read TransactionSingle Write Transaction Processor Local Bus InterfacePLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address SpaceEthernet Audio Video End Point Configuration Registers Ethernet AVB Endpoint Address SpaceRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address SpaceRx PTP Packet Control Register Rx Filtering Control RegisterTx Arbiter Idle Slope Control Register Tx Arbiter Send Slope Control RegisterRTC Offset Control Registers RTC Increment Value Control Register Current RTC Value RegistersRTC Interrupt Clear Register Software Reset Register Phase Adjustment RegisterPTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access DescriptionTri-Mode Ethernet MAC Address Space MAC Configuration and StatisticsMAC Address Filter Registers MAC Mdio Registers 102 Constraining the Core Required ConstraintsPeriod Constraints for Clock Nets PLBclkHostclk TxclkRtcclk Timespecs for Critical Logic within the CoreRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System IntegrationTri-Mode Ethernet MAC Core Generation LogiCORE IP Tri-Mode Ethernet MAC Soft CoreSystem Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics114 Connections Including Ethernet Statistics GNDLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLBUsing an ISE Software Top-Level Project PLBEthernet AVB Endpoint User Guide 123 Xpslltemac configuration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACIntroduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemacEthernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MACEND Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock MasterClock Slave Software System IntegrationDriver Instantiation Software DriversInterrupt Service Routine Connections Software System IntegrationEthernet AVB Endpoint Setup When Using a LogiCORE IP Tri-Mode Ethernet MACCore Initialization System-Specific Defines in xavbhw.hSetting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback HandlerStarting and Stopping the AVB Drivers Quick Start Example Design OverviewQuick Start Example Design 1Ethernet AVB Endpoint Example Design and Test BenchGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Setting up for Simulation Functional Simulation Implementing the Example DesignSimulating the Example Design Implementing the Example DesignWhat’s Next? Timing SimulationDetailed Example Design Standard Format Project directoryDirectory and File Contents Component name/doc Project directory/component nameComponent name/example design Component name/implement 5Implement Directory Name DescriptionImplement/results Component name/simulationSimulation/functional 6Results Directory Name DescriptionSimulation/timing Name DescriptionComponentname/drivers/v204a Drivers/avbv204a/dataDrivers/avbv204a/examples 11Driver Example Directory Name DescriptionDrivers/avbv204a/src Simulation Scripts Implementation ScriptsImplementation Scripts Example Design Example Design HDL for the Ethernet AVB EndpointEthernet Frame Stimulus Top-Level Example Design HDLExample Design Ethernet Frame Checker Loopback ModulePLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test BenchSimulation Run Time Customizing the Test BenchChanging Frame Data 3Simulator Wave Window Contents Viewing the Simulation Wave FormDetailed Example Design EDK format Detailed Example Design EDK format MyProcessorIPLib/pcores/ethavbendpointv204a Component name/MyProcessorIPLibPcores/ethavbendpointv204a/data Pcores/ethavbendpointv204a/hdl/vhdl Pcores/ethavbendpointv204a/netlistMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Time Stamp Accuracy RTC Real Time Instantaneous ErrorTime Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp AccuracyRTC Sampling Error Time Stamp AccuracyFigure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy172