
Chapter 16: Detailed Example Design (EDK format)
Directory and File Contents
The core directories and their associated files are defined in the following tables.
<project directory>
The project directory contains all the CORE Generator software project files.
Table
Name |
| Description |
|
|
|
| <project_dir> | |
|
|
|
<component_name>.ngc |
| |
|
| the Verilog or VHDL example design. |
|
|
|
<component_name>.xco |
| Log file that records the settings used to |
|
| generate a core. An XCO file is |
|
| generated by the CORE Generator |
|
| software for each core that it creates in |
|
| the current project directory. An XCO |
|
| file can also be used as an input to the |
|
| CORE Generator software. |
|
|
|
<component_name>_flist.txt |
| List of files delivered with the core. |
|
|
|
Back to Top |
|
|
<project directory>/<component name>
The <component name> directory contains the release notes file provided with the core, which may include
Table
Name | Description |
|
|
<project_dir>/<component_name> | |
|
|
eth_avb_endpoint_readme.txt | Core release notes file. |
|
|
Back to Top |
|
160 | www.xilinx.com | Ethernet AVB Endpoint User Guide |
|
| UG492 July 23, 2010 |