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Xilinx UG492 manual Conventions Acronym Spelled Out, Vhdl

Models: UG492

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Conventions

Acronym	Spelled Out

PHY	physical-side interface

PHYAD	Physical Address

PLB	Processor Local Bus

PTP	Precise Timing Protocol

REGAD	Register Address

RTC	Real Time Clock

RO	Read Only

R/W	Read/Write

Rx	Receive

SFD	Start of Frame Delimiter

SRP	Stream Reservation Protocol

TEMAC	Tri-Mode Ethernet MAC

TCP/IP	Transmission Control Protocol / Internet Protocol.

TOE	TCP/IP Offload Engine

Tx	Transmitter

UCF	User Constraints File

us	microseconds

VHDL	VHSIC Hardware Description Language
	(VHSIC an acronym for Very High-Speed Integrated Circuits)

VLAN	Virtual LAN (Local Area Network)

WO	Write Only

XCO	Xilinx CORE Generator core source file

XPS	Xilinx Platform Studio (part of the EDK software)

XPS_LL_TEMAC	XPS LocalLink Tri-Mode Ethernet MAC

Ethernet AVB Endpoint User Guide

www.xilinx.com

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UG492 July 23, 2010

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Xilinx UG492 manual Conventions Acronym Spelled Out, Vhdl

Contents

UG492 July 23 LogiCORETM IP Ethernet AVB EndpointDate Version Revision Revision HistoryTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide 1Example AVB Home Network Schedule of FiguresConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide About This Guide Guide ContentsTypographical ConventionsOnline Document ConventionsConvention Meaning or Use Example Acronym Spelled Out List of AbbreviationsVhdl Conventions Acronym Spelled OutPreface About This Guide System Requirements IntroductionAbout the Core WindowsAdditional Core Resources Recommended Design ExperienceTechnical Support FeedbackFeedback DocumentIntroduction Before you Begin License Options Licensing the CoreSimulation Only Full System Hardware EvaluationObtaining Your License Key Installing the License File1Example AVB Home Network Overview of Ethernet Audio Video BridgingAVB Specifications P802.1ASOverview of Ethernet Audio Video Bridging P802.1Qav AVB SpecificationsTalker Assumptions Listener AssumptionsP802.1Qat Typical ImplementationTypical Implementation UG492 July 23 Ethernet AVB GUI Generating the CoreComponent Name Core Delivery FormatGenerating the Core Number of PLB Masters PLB Base AddressEthernet AVB GUI Output Generation Parameter Values in the XCO FileCore Architecture Core Architecture Standard Core Generator FormatEDK pcore Format EDK pcore FormatPLB Interface Functional Block DescriptionAV Traffic Interface Legacy Traffic InterfaceRx Splitter Tx ArbiterMAC Header Filters Functional Block DescriptionTx PTP Packet Buffers Precise Timing Protocol BlocksTx Time Stamp Rx PTP Packet BuffersRTC Tri-Mode Ethernet MACs Software Drivers1Clocks and Resets Signal Direction Description Clocks and ResetCore Interfaces Core InterfacesLegacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals3Legacy Traffic Signals Receiver Path Direction Description AV Traffic Transmitter Path Signals 3Legacy Traffic Signals Receiver Path4AV Traffic Signals Transmitter Path Direction Description 5AV Traffic Signals Receiver Path Direction Description AV Traffic Receiver Path SignalsTri-Mode Ethernet MAC Client Interface MAC Transmitter InterfaceMAC Management Interface MAC Receiver InterfaceProcessor Local Bus PLB Interface PIN Name Direction Description PLB InterfaceEthernet AVB Endpoint User Guide 10Interrupt Signals Direction Description Interrupt SignalsSignal Direction Description PTP SignalsTx Legacy Traffic I/F Ethernet AVB Endpoint TransmissionEthernet AVB Endpoint Transmission Error Free Legacy Frame TransmissionErrored Legacy Frame Transmission Tx AV Traffic I/FTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Overview Tx ArbiterCredit Based Traffic Shaping Algorithm Tx Arbiter4Credit-based Shaper Operation Tx Arbiter Bandwidth Control IdleSlopeSendSlope LoLimit HiLimitEthernet AVB Endpoint Reception Rx SplitterRx Legacy Traffic I/F Ethernet AVB Endpoint Reception Error Free Legacy Frame ReceptionLegacy MAC Header Filters Errored Legacy Frame ReceptionOverview of Operation Rx Legacy Traffic I/F3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Full Destination Address DA Match Single MAC Header Filter Usage Examples5Filtering of Frames with a Partial DA Match Partial Destination Address DA MatchAny Other Combinations Vlan Priority MatchError Free AV Traffic Reception Rx AV Traffic I/FRx AV Traffic I/F 8Errored Frame Reception across the AV Traffic Interface Errored AV Traffic ReceptionReal Time Clock Real Time Clock and Time StampingReal Time Clock and Time Stamping RTC Implementation Increment of Nanoseconds FieldReal Time Clock Increment of the Seconds Field Controlled Frequency RTCSynchronized RTC Time Stamping Logic Time Stamping Logic3Time Stamping Position Time Stamp Sampling Position of MAC FramesIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers1Tx PTP Packet Buffer Structure Precise Timing Protocol Packet BuffersRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Configuration and Status Processor Local Bus InterfaceSingle Read Transaction 1Single Read Transaction Configuration and StatusProcessor Local Bus Interface Single Write TransactionPLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space PLB Address Map and Register DefinitionsEthernet AVB Endpoint Address Space Ethernet Audio Video End Point Configuration RegistersRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address SpaceRx Filtering Control Register Rx PTP Packet Control RegisterTx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control RegisterRTC Offset Control Registers Current RTC Value Registers RTC Increment Value Control RegisterRTC Interrupt Clear Register Phase Adjustment Register Software Reset RegisterPTP Receiver logic reset. When written with a Address Default Access Description 16MAC Header Filter Configuration Registers Cont’dMAC Configuration and Statistics Tri-Mode Ethernet MAC Address SpaceMAC Address Filter Registers MAC Mdio Registers 102 Required Constraints Constraining the CorePLBclk Period Constraints for Clock NetsHostclk TxclkTimespecs for Critical Logic within the Core RtcclkRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACsLogiCORE IP Tri-Mode Ethernet MAC Soft Core Tri-Mode Ethernet MAC Core GenerationSystem Integration Connections Without Ethernet Statistics Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs114 GND Connections Including Ethernet StatisticsLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 PLB Using an EDK Project Top LevelPLB Using an ISE Software Top-Level ProjectEthernet AVB Endpoint User Guide 123 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Xpslltemac configurationIntroduction System Overview AVB capable xpslltemac Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACEthernet AVB Endpoint Connections 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC MHS File SyntaxEND Ethernet AVB Endpoint User Guide 129 130 Clock Master Software DriversSoftware System Integration Clock SlaveDriver Instantiation Software DriversSoftware System Integration Interrupt Service Routine ConnectionsWhen Using a LogiCORE IP Tri-Mode Ethernet MAC Ethernet AVB Endpoint SetupCore Initialization System-Specific Defines in xavbhw.hSetting up GrandMaster Discontinuity Callback Handler Setting up SourcePortIdentity and Default TX PTP MessagesStarting and Stopping the AVB Drivers Overview Quick Start Example Design1Ethernet AVB Endpoint Example Design and Test Bench Quick Start Example DesignGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Implementing the Example Design Setting up for Simulation Functional SimulationSimulating the Example Design Implementing the Example DesignTiming Simulation What’s Next?Project directory Detailed Example Design Standard FormatDirectory and File Contents Project directory/component name Component name/docComponent name/example design 5Implement Directory Name Description Component name/implementComponent name/simulation Implement/resultsSimulation/functional 6Results Directory Name DescriptionName Description Simulation/timingDrivers/avbv204a/data Componentname/drivers/v204aDrivers/avbv204a/examples 11Driver Example Directory Name DescriptionDrivers/avbv204a/src Implementation Scripts Simulation ScriptsImplementation Scripts Example Design HDL for the Ethernet AVB Endpoint Example DesignTop-Level Example Design HDL Ethernet Frame StimulusExample Design Loopback Module Ethernet Frame CheckerPLB Module 2Ethernet AVB Endpoint Demonstration Test Bench Demonstration Test BenchCustomizing the Test Bench Simulation Run TimeChanging Frame Data Viewing the Simulation Wave Form 3Simulator Wave Window ContentsDetailed Example Design EDK format Detailed Example Design EDK format Component name/MyProcessorIPLib MyProcessorIPLib/pcores/ethavbendpointv204aPcores/ethavbendpointv204a/data Pcores/ethavbendpointv204a/netlist Pcores/ethavbendpointv204a/hdl/vhdlMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Real Time Instantaneous Error RTC Time Stamp AccuracyTime Stamp Accuracy Appendix a RTC Time Stamp Accuracy Figure A-1RTC Periodic ErrorTime Stamp Accuracy RTC Sampling ErrorFigure A-3Sampling Position Uncertainty Figure A-4Overall Time Stamp Accuracy Accuracy Resulting from the Combined Errors172