Chapter 11: Constraining the Core
INST "*top/rx_rtc_sample_inst/sample_taken_toggle" TNM = FFS "rx_sample_taken";
INST "*top/rx_rtc_sample_inst/resync_sample_taken_toggle/data_sync" TNM = FFS "rx_sample_taken_resync";
TIMESPEC "ts_rx_sample_taken" = FROM "rx_sample_taken" TO "rx_sample_taken_resync" TIG;
INST "*top/rx_rtc_sample_inst/timestamp*" TNM = FFS "rx_timestamp";
TIMESPEC "ts_rx_timestamp_route" = FROM "rx_timestamp" TO "FFS" 8 ns
DATAPATHONLY;
#clock domain crossing constraints for Rx PTP Packet Buffer logic
INST
"*top/ptp_packet_buffer_inst/rx_ptp_packet_buffer_inst/rx_mac_logic_in st/rx_clear_toggle" TNM = FFS "rx_clear_toggle";
INST
"*top/ptp_packet_buffer_inst/rx_ptp_packet_buffer_inst/rx_mac_logic_in st/resync_clear_toggle/data_sync" TNM = FFS "rx_clear_toggle_resync"; TIMESPEC "ts_rx_clear_toggle" = FROM "rx_clear_toggle" TO "rx_clear_toggle_resync" TIG;
INST
"*top/ptp_packet_buffer_inst/rx_ptp_packet_buffer_inst/rx_mac_logic_in st/address*" TNM = FFS "rx_buf_addr";
INST
"*top/ptp_packet_buffer_inst/rx_ptp_packet_buffer_inst/rx_mac_logic_in st/rx_packet*" TNM = FFS "rx_buf_addr_sample";
TIMESPEC "ts_rx_buf_addr" = FROM "rx_buf_addr" TO "rx_buf_addr_sample" 64 ns DATAPATHONLY;
#clock domain crossing constraints for Tx PTP Packet Buffer logic
INST
"*top/ptp_packet_buffer_inst/tx_ptp_packet_buffer_inst/tx_mac_logic_in st/tx_valid_reg2" TNM = FFS "tx_valid_reg2";
INST
"*top/ptp_packet_buffer_inst/tx_ptp_packet_buffer_inst/tx_mac_logic_in st/resync_frame_tx_toggle/data_sync" TNM = FFS "tx_valid_reg2_resync"; TIMESPEC "ts_tx_valid_reg2" = FROM "tx_valid_reg2" TO "tx_valid_reg2_resync" TIG;
#clock domain crossing constraints for Rx Configuration
INST "*top/avb_configuration_inst/promiscuous_mode_int" TNM = FFS "promiscuous_mode";
INST
"*top/legacy_inst*address_filter_inst/*resync_promiscuous_mode/data_sy nc" TNM = FFS "promiscuous_mode_resync";
TIMESPEC "ts_promiscuous_mode" = FROM "promiscuous_mode" TO "promiscuous_mode_resync" TIG;
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| UG492 July 23, 2010 |