Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice.

XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.

© 2008-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license.All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

9/18/08

v1.1

Initial Xilinx release; ISE® 10.1, Update 3.

 

 

 

4/24/09

v1.2

Updated to version 1.2 of the core; Xilinx tools 11.1.

 

 

 

6/24/09

v2.1

Updated to version 2.1 of the core; Xilinx tools 11.2.

 

 

 

9/16/09

v2.2

Updated to version 2.2 of the core; Xilinx tools 11.3.

 

 

 

4/19/10

v2.3

Updated to version 2.3 of the core; Xilinx tools 12.1.

 

 

 

7/23/10

v2.4

Updated to version 2.4 of the core; Xilinx tools 12.2.

 

 

Added four chapters from the Getting Started Guide to this User Guide:

 

 

• Licensing the Core

 

 

• Quick Start Example Design

 

 

• Detailed Example Design (Standard Format)

 

 

• Detailed Example Design (EDK format)

 

 

The Getting Started Guide is being discontinued in this release.

 

 

 

Ethernet AVB Endpoint User Guide

www.xilinx.com

UG492 July 23, 2010

Page 2
Image 2
Xilinx UG492 manual Revision History, Date Version Revision