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Xilinx UG492 manual PLB Interface, PIN Name Direction Description

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Core Interfaces

PLB Interface

Table 5-9defines the signals on the PLB bus. For detailed information, see the IBM PLB specification. Shaded rows represent signals not used by this core; inputs are ignored and outputs are tied to a constant. These signals are synchronous to PLB_clk; see “Clocks and Resets” for additional information.

Table 5-9: PLB Signals

PIN Name	Direction	Description

PLB_clk	Input	Reference clock for the PLB

PLB_reset	Input	Reset for the PLB, synchronous to
		PLB_clk

PLB_ABus[0:31]	input	PLB address bus

PLB_UABus[0:31]	Input	PLB upper address bus

PLB_PAvaild	Input	PLB primary address valid indicator

PLB_SAValid	Input	Unused. PLB secondary address valid
		indicator.

PLB_rdPrim	Input	Unused. PLB secondary to primary read
		request indicator.

PLB_wrPrim	Input	Unused. PLB secondary to primary write
		request indicator.

PLB_masterID	Input	PLB current master identifier
[0:log2(NUM_MASTERS)]

PLB_abort	Input	PLB abort request indicator

PLB_busLock	Input	Unused. PLB bus lock.

PLB_RNW	Input	PLB read not write

PLB_BE[0:3]	Input	PLB byte enables

PLB_MSize[0:1]	Input	PLB master data bus size

PLB_size[0:3]	Input	PLB transfer size. Only support size 0.

PLB_type[0:2]	Input	PLB transfer type. Only support type 0.

PLB_TAttribute[0:15]	Input	Unused. PLB transfer attribute bus.

PLB_lockErr	Input	Unused. PLB lock error indicator.

PLB_wrDBus[0:31]	Input	PLB write data bus

PLB_wrBurst	Input	PLB write burst transfer indicator.

PLB_rdBurst	Input	PLB read burst transfer indicator.

PLB_rdPendReq	Input	Unused. PLB pending read request
		priority.

PLB_wrPendReq	Input	Unused. PLB pending write request
		priority.

PLB_rdPendPri[0:1]	Input	Unused. PLB pending read bus request
		indicator.

Ethernet AVB Endpoint User Guide

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UG492 July 23, 2010

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Xilinx UG492 manual PLB Interface, PIN Name Direction Description

Contents

UG492 July 23 LogiCORETM IP Ethernet AVB EndpointDate Version Revision Revision HistoryTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide 1Example AVB Home Network Schedule of FiguresConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide About This Guide Guide ContentsTypographical ConventionsConvention Meaning or Use Example Online DocumentConventions Acronym Spelled Out List of AbbreviationsVhdl Conventions Acronym Spelled OutPreface About This Guide System Requirements IntroductionAbout the Core WindowsAdditional Core Resources Recommended Design ExperienceTechnical Support FeedbackFeedback DocumentIntroduction Before you Begin License Options Licensing the CoreSimulation Only Full System Hardware EvaluationObtaining Your License Key Installing the License File1Example AVB Home Network Overview of Ethernet Audio Video BridgingOverview of Ethernet Audio Video Bridging AVB SpecificationsP802.1AS P802.1Qav AVB SpecificationsTalker Assumptions Listener AssumptionsP802.1Qat Typical ImplementationTypical Implementation UG492 July 23 Ethernet AVB GUI Generating the CoreGenerating the Core Component NameCore Delivery Format Ethernet AVB GUI Number of PLB MastersPLB Base Address Output Generation Parameter Values in the XCO FileCore Architecture Core Architecture Standard Core Generator FormatEDK pcore Format EDK pcore FormatPLB Interface Functional Block DescriptionAV Traffic Interface Legacy Traffic InterfaceRx Splitter Tx ArbiterMAC Header Filters Functional Block DescriptionTx PTP Packet Buffers Precise Timing Protocol BlocksTx Time Stamp Rx PTP Packet BuffersRTC Tri-Mode Ethernet MACs Software Drivers1Clocks and Resets Signal Direction Description Clocks and ResetCore Interfaces Core Interfaces3Legacy Traffic Signals Receiver Path Direction Description Legacy Traffic Transmitter Path SignalsLegacy Traffic Receiver Path Signals 4AV Traffic Signals Transmitter Path Direction Description AV Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path 5AV Traffic Signals Receiver Path Direction Description AV Traffic Receiver Path SignalsTri-Mode Ethernet MAC Client Interface MAC Transmitter InterfaceMAC Management Interface MAC Receiver InterfaceProcessor Local Bus PLB Interface PIN Name Direction Description PLB InterfaceEthernet AVB Endpoint User Guide 10Interrupt Signals Direction Description Interrupt SignalsSignal Direction Description PTP SignalsTx Legacy Traffic I/F Ethernet AVB Endpoint TransmissionEthernet AVB Endpoint Transmission Error Free Legacy Frame TransmissionTx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Overview Tx ArbiterCredit Based Traffic Shaping Algorithm Tx Arbiter4Credit-based Shaper Operation SendSlope Tx Arbiter Bandwidth ControlIdleSlope LoLimit HiLimitRx Legacy Traffic I/F Ethernet AVB Endpoint ReceptionRx Splitter Ethernet AVB Endpoint Reception Error Free Legacy Frame ReceptionLegacy MAC Header Filters Errored Legacy Frame ReceptionOverview of Operation Rx Legacy Traffic I/F3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Full Destination Address DA Match Single MAC Header Filter Usage Examples5Filtering of Frames with a Partial DA Match Partial Destination Address DA MatchAny Other Combinations Vlan Priority MatchRx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F 8Errored Frame Reception across the AV Traffic Interface Errored AV Traffic ReceptionReal Time Clock Real Time Clock and Time StampingReal Time Clock and Time Stamping Real Time Clock RTC ImplementationIncrement of Nanoseconds Field Synchronized RTC Increment of the Seconds FieldControlled Frequency RTC Time Stamping Logic Time Stamping Logic3Time Stamping Position Time Stamp Sampling Position of MAC FramesIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers1Tx PTP Packet Buffer Structure Precise Timing Protocol Packet BuffersRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Single Read Transaction Configuration and StatusProcessor Local Bus Interface 1Single Read Transaction Configuration and StatusProcessor Local Bus Interface Single Write TransactionPLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space PLB Address Map and Register DefinitionsEthernet AVB Endpoint Address Space Ethernet Audio Video End Point Configuration RegistersRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address SpaceRx Filtering Control Register Rx PTP Packet Control RegisterRTC Offset Control Registers Tx Arbiter Send Slope Control RegisterTx Arbiter Idle Slope Control Register Current RTC Value Registers RTC Increment Value Control RegisterRTC Interrupt Clear Register Phase Adjustment Register Software Reset RegisterPTP Receiver logic reset. When written with a Address Default Access Description 16MAC Header Filter Configuration Registers Cont’dMAC Address Filter Registers MAC Configuration and StatisticsTri-Mode Ethernet MAC Address Space MAC Mdio Registers 102 Required Constraints Constraining the CorePLBclk Period Constraints for Clock NetsHostclk TxclkRequired Constraints Timespecs for Critical Logic within the CoreRtcclk Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACsSystem Integration LogiCORE IP Tri-Mode Ethernet MAC Soft CoreTri-Mode Ethernet MAC Core Generation Connections Without Ethernet Statistics Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs114 GND Connections Including Ethernet StatisticsLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 PLB Using an EDK Project Top LevelPLB Using an ISE Software Top-Level ProjectEthernet AVB Endpoint User Guide 123 Introduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACXpslltemac configuration System Overview AVB capable xpslltemac Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACEthernet AVB Endpoint Connections 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC MHS File SyntaxEND Ethernet AVB Endpoint User Guide 129 130 Clock Master Software DriversSoftware System Integration Clock SlaveDriver Instantiation Software DriversSoftware System Integration Interrupt Service Routine ConnectionsWhen Using a LogiCORE IP Tri-Mode Ethernet MAC Ethernet AVB Endpoint SetupCore Initialization System-Specific Defines in xavbhw.hSetting up GrandMaster Discontinuity Callback Handler Setting up SourcePortIdentity and Default TX PTP MessagesStarting and Stopping the AVB Drivers Overview Quick Start Example Design1Ethernet AVB Endpoint Example Design and Test Bench Quick Start Example DesignGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Implementing the Example Design Setting up for Simulation Functional SimulationSimulating the Example Design Implementing the Example DesignTiming Simulation What’s Next?Project directory Detailed Example Design Standard FormatDirectory and File Contents Component name/example design Project directory/component nameComponent name/doc 5Implement Directory Name Description Component name/implementComponent name/simulation Implement/resultsSimulation/functional 6Results Directory Name DescriptionName Description Simulation/timingDrivers/avbv204a/data Componentname/drivers/v204aDrivers/avbv204a/examples 11Driver Example Directory Name DescriptionDrivers/avbv204a/src Implementation Scripts Implementation ScriptsSimulation Scripts Example Design HDL for the Ethernet AVB Endpoint Example DesignExample Design Top-Level Example Design HDLEthernet Frame Stimulus Loopback Module Ethernet Frame CheckerPLB Module 2Ethernet AVB Endpoint Demonstration Test Bench Demonstration Test BenchChanging Frame Data Customizing the Test BenchSimulation Run Time Viewing the Simulation Wave Form 3Simulator Wave Window ContentsDetailed Example Design EDK format Detailed Example Design EDK format Pcores/ethavbendpointv204a/data Component name/MyProcessorIPLibMyProcessorIPLib/pcores/ethavbendpointv204a Pcores/ethavbendpointv204a/netlist Pcores/ethavbendpointv204a/hdl/vhdlMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 Time Stamp Accuracy RTC Real Time Instantaneous ErrorRTC Time Stamp Accuracy Appendix a RTC Time Stamp Accuracy Figure A-1RTC Periodic ErrorTime Stamp Accuracy RTC Sampling ErrorFigure A-3Sampling Position Uncertainty Figure A-4Overall Time Stamp Accuracy Accuracy Resulting from the Combined Errors172