Core Architecture | Xilinx UG492 guide

Chapter 5

Core Architecture

As described in Chapter 4, “Generating the Core”, the core can be generated in one of two formats, the functionality of which is described in this chapter:

•“Standard CORE Generator Format” (provided for the standard ISE® software environment)

This option will deliver the core in the standard CORE Generator™ output format, as used by many other cores including previous versions of this core and all other Ethernet LogiCORE™ IP solutions.

When generated in this format, the core is designed to interface to the LogiCORE IP Tri-Mode Ethernet MAC or the LogiCORE IP Embedded Tri-Mode Ethernet MAC wrappers (available in selected Virtex® families). See Figure 5-1.

•“EDK pcore Format”(provided for the Embedded Development Kit)

This option will deliver the core in the standard pcore format, suitable for directly importing into the Xilinx Embedded Development Kit (EDK) environment.

When generated in this format, the core is designed to interface to the XPS LocalLink Tri-Mode Ethernet MAC (xps_ll_temac). See Figure 5-2.

Ethernet AVB Endpoint User Guide

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UG492 July 23, 2010

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Xilinx UG492 manual Core Architecture

Contents

UG492 July 23 LogiCORETM IP Ethernet AVB Endpoint Date Version Revision Revision History Table of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide 1Example AVB Home Network Schedule of Figures Constraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide About This Guide Guide Contents Typographical Conventions Online Document ConventionsConvention Meaning or Use Example Acronym Spelled Out List of Abbreviations Vhdl Conventions Acronym Spelled Out Preface About This Guide Windows IntroductionSystem Requirements About the Core Feedback Recommended Design ExperienceAdditional Core Resources Technical Support Feedback Document Introduction Full System Hardware Evaluation Licensing the CoreBefore you Begin License Options Simulation Only Obtaining Your License Key Installing the License File 1Example AVB Home Network Overview of Ethernet Audio Video Bridging AVB Specifications P802.1ASOverview of Ethernet Audio Video Bridging Listener Assumptions AVB SpecificationsP802.1Qav Talker Assumptions P802.1Qat Typical Implementation Typical Implementation UG492 July 23 Ethernet AVB GUI Generating the Core Component Name Core Delivery FormatGenerating the Core Number of PLB Masters PLB Base AddressEthernet AVB GUI Output Generation Parameter Values in the XCO File Core Architecture Core Architecture Standard Core Generator Format EDK pcore Format EDK pcore Format Legacy Traffic Interface Functional Block DescriptionPLB Interface AV Traffic Interface Functional Block Description Tx ArbiterRx Splitter MAC Header Filters Rx PTP Packet Buffers Precise Timing Protocol BlocksTx PTP Packet Buffers Tx Time Stamp RTC Tri-Mode Ethernet MACs Software Drivers Core Interfaces Clocks and Reset1Clocks and Resets Signal Direction Description Core Interfaces Legacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals3Legacy Traffic Signals Receiver Path Direction Description AV Traffic Transmitter Path Signals 3Legacy Traffic Signals Receiver Path4AV Traffic Signals Transmitter Path Direction Description MAC Transmitter Interface AV Traffic Receiver Path Signals5AV Traffic Signals Receiver Path Direction Description Tri-Mode Ethernet MAC Client Interface MAC Management Interface MAC Receiver Interface Processor Local Bus PLB Interface PIN Name Direction Description PLB Interface Ethernet AVB Endpoint User Guide 10Interrupt Signals Direction Description Interrupt Signals Signal Direction Description PTP Signals Tx Legacy Traffic I/F Ethernet AVB Endpoint Transmission Ethernet AVB Endpoint Transmission Error Free Legacy Frame Transmission Errored Legacy Frame Transmission Tx AV Traffic I/FTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Tx Arbiter Tx ArbiterOverview Credit Based Traffic Shaping Algorithm 4Credit-based Shaper Operation Tx Arbiter Bandwidth Control IdleSlopeSendSlope LoLimit HiLimit Ethernet AVB Endpoint Reception Rx SplitterRx Legacy Traffic I/F Ethernet AVB Endpoint Reception Error Free Legacy Frame Reception Rx Legacy Traffic I/F Errored Legacy Frame ReceptionLegacy MAC Header Filters Overview of Operation 3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Full Destination Address DA Match Single MAC Header Filter Usage Examples 5Filtering of Frames with a Partial DA Match Partial Destination Address DA Match Any Other Combinations Vlan Priority Match Error Free AV Traffic Reception Rx AV Traffic I/FRx AV Traffic I/F 8Errored Frame Reception across the AV Traffic Interface Errored AV Traffic Reception Real Time Clock Real Time Clock and Time Stamping Real Time Clock and Time Stamping RTC Implementation Increment of Nanoseconds FieldReal Time Clock Increment of the Seconds Field Controlled Frequency RTCSynchronized RTC Time Stamping Logic Time Stamping Logic 3Time Stamping Position Time Stamp Sampling Position of MAC Frames IEEE1722 Real Time Clock Format IEEE1722 Real Time Clock Format Real Time Clock and Time Stamping Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer Structure Precise Timing Protocol Packet Buffers Rx PTP Packet Buffer Rx PTP Packet Buffer 2Rx PTP Packet Buffer Configuration and Status Processor Local Bus InterfaceSingle Read Transaction 1Single Read Transaction Configuration and Status Processor Local Bus Interface Single Write Transaction PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space PLB Address Map and Register Definitions Tx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration RegistersEthernet AVB Endpoint Address Space Rx PTP Packet Buffer Address Space Rx Filtering Control Register Rx PTP Packet Control Register Tx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control RegisterRTC Offset Control Registers Current RTC Value Registers RTC Increment Value Control Register RTC Interrupt Clear Register Phase Adjustment Register Software Reset Register PTP Receiver logic reset. When written with a Address Default Access Description 16MAC Header Filter Configuration Registers Cont’d MAC Configuration and Statistics Tri-Mode Ethernet MAC Address SpaceMAC Address Filter Registers MAC Mdio Registers 102 Required Constraints Constraining the Core Txclk Period Constraints for Clock NetsPLBclk Hostclk Timespecs for Critical Logic within the Core RtcclkRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs LogiCORE IP Tri-Mode Ethernet MAC Soft Core Tri-Mode Ethernet MAC Core GenerationSystem Integration Connections Without Ethernet Statistics Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs 114 GND Connections Including Ethernet Statistics LogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 PLB Using an EDK Project Top Level PLB Using an ISE Software Top-Level Project Ethernet AVB Endpoint User Guide 123 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Xpslltemac configurationIntroduction System Overview AVB capable xpslltemac Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Ethernet AVB Endpoint Connections 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC MHS File Syntax END Ethernet AVB Endpoint User Guide 129 130 Clock Master Software Drivers Software Drivers Clock SlaveSoftware System Integration Driver Instantiation Software System Integration Interrupt Service Routine Connections System-Specific Defines in xavbhw.h Ethernet AVB Endpoint SetupWhen Using a LogiCORE IP Tri-Mode Ethernet MAC Core Initialization Setting up GrandMaster Discontinuity Callback Handler Setting up SourcePortIdentity and Default TX PTP Messages Starting and Stopping the AVB Drivers Overview Quick Start Example Design 1Ethernet AVB Endpoint Example Design and Test Bench Quick Start Example Design Generating the Core 2Ethernet AVB Endpoint Core Customization Screen Implementing the Example Design Setting up for Simulation Functional SimulationImplementing the Example Design Simulating the Example Design Timing Simulation What’s Next? Project directory Detailed Example Design Standard Format Directory and File Contents Project directory/component name Component name/docComponent name/example design 5Implement Directory Name Description Component name/implement 6Results Directory Name Description Implement/resultsComponent name/simulation Simulation/functional Name Description Simulation/timing 11Driver Example Directory Name Description Componentname/drivers/v204aDrivers/avbv204a/data Drivers/avbv204a/examples Drivers/avbv204a/src Implementation Scripts Simulation ScriptsImplementation Scripts Example Design HDL for the Ethernet AVB Endpoint Example Design Top-Level Example Design HDL Ethernet Frame StimulusExample Design Loopback Module Ethernet Frame Checker PLB Module 2Ethernet AVB Endpoint Demonstration Test Bench Demonstration Test Bench Customizing the Test Bench Simulation Run TimeChanging Frame Data Viewing the Simulation Wave Form 3Simulator Wave Window Contents Detailed Example Design EDK format Detailed Example Design EDK format Component name/MyProcessorIPLib MyProcessorIPLib/pcores/ethavbendpointv204aPcores/ethavbendpointv204a/data 5Driver Data Directory Name Description Pcores/ethavbendpointv204a/hdl/vhdlPcores/ethavbendpointv204a/netlist MyProcessorIPLib/drivers/avbv204a 8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Real Time Instantaneous Error RTC Time Stamp AccuracyTime Stamp Accuracy Appendix a RTC Time Stamp Accuracy Figure A-1RTC Periodic Error Time Stamp Accuracy RTC Sampling Error Figure A-3Sampling Position Uncertainty Figure A-4Overall Time Stamp Accuracy Accuracy Resulting from the Combined Errors 172