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Chapter 15: Detailed Example Design (Standard Format)
Demonstration Test Bench
Figure 15-2 illustrates the Ethernet AVB Endpoint demonstration test bench, a simple VHDL or Verilog program for exercising the example design and the core.
Demonstration Test Bench
Clock
and
Reset
generation
Statistic
Gathering
Example Design Top Level |
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Tx frame | AV traffic |
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stimulus |
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Tx frame |
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| loopback |
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stimulus |
| Ethernet | |
| legacy |
| AVB |
| traffic | Endpoint | |
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| LogiCORE | |
Rx frame | legacy |
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traffic |
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checker |
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Rx frame |
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checker | AV traffic |
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| Interrupts | PLB | |
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| PLB |
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| module |
Figure 15-2: Ethernet AVB Endpoint Demonstration Test Bench
The following files describe the top level of the demonstration test bench:
VHDL
<project_dir>/<component_name>/simulation/demo_tb.vhd
Verilog
<project_dir>/<component_name>/simulation/demo_tb.v
The
•The number of PTP frames transmitted and received
•The number of AV frames transmitted and received
•The number of legacy frames transmitted and received.
All transmitted frame statistics should exactly match the received frame statistics for each particular frame type; if this is not the case, an error message is issued.
•Finally, the test bench estimates the percentage of overall Ethernet line rate consumed by each of the three types. This should illustrate the bandwidth policing functionality of the core, which should only allow the AV frames to consume a maximum of 75% of the overall bandwidth.
156 | www.xilinx.com | Ethernet AVB Endpoint User Guide |
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| UG492 July 23, 2010 |