Xilinx UG492 manual 16MAC Header Filter Configuration Registers Cont’d

			PLB Address Map and Register Definitions
Table 10-16:MAC Header Filter Configuration Registers (Cont’d)
Address	Default	Access	Description
PLB_base_address	0x00000000	R/W	Match Pattern: Ethernet frame bits 96 to 127
+ 0x3000			32 bit pattern to match against the Ethernet
+ (filter# * 0x20)			frame bits 96 to 127.
+ 0xC			For frames with a VLAN tag, match pattern
			bits[31:0] can be matched against the full
			VLAN field.
			For frames without a VLAN, match pattern
			bits[15:0] can be matched against the
			Length/Type field.
PLB_base_address	0xFFFFFFFF	R/W	Match Enable: Ethernet frame bits 0 to 31
+ 0x3000			There is a 1-to-1 correspondence between all
+ (filter# * 0x20)			bits in this register and all bits in the "Match
			Pattern: Ethernet frame bits 0 to 31" register.
+ 0x10
			For each bit:
			logic 1 enables the match: the corresponding
			bit in the Match Pattern will be compared
			logic 0 disables the match: the corresponding
			bit in the Match Pattern will be a don’t-care.
PLB_base_address	0x0000FFFF	R/W	Match Enable: Ethernet frame bits 32 to 63
+ 0x3000			There is a 1-to-1 correspondence between all
+ (filter# * 0x20)			bits in this register and all bits in the "Match
			Pattern: Ethernet frame bits 32 to 63" register.
+ 0x14
			For each bit:
			logic 1 enables the match: the corresponding
			bit in the Match Pattern will be compared
			logic 0 disables the match: the corresponding
			bit in the Match Pattern will be a don’t-care.
PLB_base_address	0x00000000	R/W	Match Enable: Ethernet frame bits 64 to 95
+ 0x3000			There is a 1-to-1 correspondence between all
+ (filter# * 0x20)			bits in this register and all bits in the "Match
			Pattern: Ethernet frame bits 64 to 95" register.
+ 0x18
			For each bit:
			logic 1 enables the match: the corresponding
			bit in the Match Pattern will be compared
			logic 0 disables the match: the corresponding
			bit in the Match Pattern will be a don’t-care.
PLB_base_address	0x00000000	R/W	Match Enable: Ethernet frame bits 96 to 127
+ 0x3000			There is a 1-to-1 correspondence between all
+ (filter# * 0x20)			bits in this register and all bits in the "Match
			Pattern: Ethernet frame bits 96 to 127" register.
+ 0x1C
			For each bit:
			logic 1 enables the match: the corresponding
			bit in the Match Pattern will be compared
			logic 0 disables the match: the corresponding
			bit in the Match Pattern will be a don’t-care.

Ethernet AVB Endpoint User Guide www.xilinx.com 99

UG492 July 23, 2010