Example Design
PLB Module
The following files describe the logic for the PLB module.
VHDL
<project_dir>/<component_name>/example_design/plb_client_logic.vhd
Verilog
<project_dir>/<component_name>/example_design/plb_client_logic.v
The PLB module connects to the PLB interface of the core and performs the following functions:
•Initialization. A state machine writes to the RTC configuration space to set the RTC running at the correct frequency following
•PTP Timer Interrupt Service Routine. When the interrupt_ptp_timer is asserted, a state machine requests transmission of a PTP sync frame, then clears the interrupt.
•PTP Transmit Interrupt Service Routine. When interrupt_ptp_tx is asserted (a PTP frame has been transmitted), the state machine reads from the PTP Tx Control/Status register to determine the type of PTP frame sent. If it was a sync frame, it then requests a
•PTP Receive Interrupt Service Routine. When interrupt_ptp_rx is asserted (a PTP frame has been received), the state machine reads from the PTP Rx Control/Status register to determine which of the PTP frame buffers the received frame will be stored in; this read also clears the interrupt. In this simple demonstration, nothing further is performed.
This functionality is related to the normal operation of a PTP clock master in that the logic results in a transmission of PTP
Note: The real intent for the PLB interface is for connection into the EDK environment; software drivers are provided to be run on an embedded processor, which performs full 802.1AS (Precise Timing Protocol (PTP)) functionality. See Chapter 13, “Software Drivers” for detailed information about the provided software drivers.
Ethernet AVB Endpoint User Guide | www.xilinx.com | 155 |
UG492 July 23, 2010
