Chapter 5: Core Architecture

Standard CORE Generator Format

AV

Traffic

Tx

Rx

.c, .h

software

drivers

Embedded PLB

Micro

Processor

Legacy

Traffic

Tx

Rx

Figure 5-1illustrates the functional blocks of the Ethernet AVB Endpoint core when it is generated in standard CORE Generator format. As illustrated, this is intended to be connected to the LogiCORE IP Tri-Mode Ethernet MAC (or to the LogiCORE IP Embedded Ethernet Wrappers available in certain Virtex devices).

Each of the functional blocks illustrated will be introduced in the following sections of this chapter. However, observe from the figure that:

The Host I/F (management interface) of the Tri-Mode Ethernet MAC is connected directly to the Ethernet AVB Endpoint LogiCORE IP. This enables the MAC to be fully configured via the “PLB Interface” of the Ethernet AVB Endpoint core.

The core provides two independent full-duplex interfaces for customer logic: the “AV Traffic Interface” and the “Legacy Traffic Interface”.

The “Legacy Traffic Interface” contains “MAC Header Filters”; these are provided to replace the Address Filter functionality of the LogiCORE IP Tri-Mode Ethernet MACs (which must be disabled).

Ethernet AVB Endpoint

 

 

 

Tx Arbiter

Tri-Mode

AV Traffic I/F

 

 

 

 

 

 

 

 

Ethernet

 

 

 

 

 

 

MAC

 

 

 

 

 

Tx Client

Tx PHY

 

 

 

 

 

 

 

 

 

 

 

 

Rx Client

Rx PHY

Precise Timing Protocol (PTP)

 

 

 

Tx PTP Packet Buffer

 

Tx Time Stamp

 

 

 

 

PLB I/F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Real Time Counter

 

 

 

Rx PTP Packet Buffer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rx Time Stamp

 

 

 

 

 

 

 

Host I/F

Legacy Traffic I/F

Rx Splitter

MAC Header Filters

Figure 5-1:Ethernet AVB Endpoint Core Block Diagram for Connection to LogiCORE IP Tri-Mode Ethernet

MAC

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Ethernet AVB Endpoint User Guide

 

 

UG492 July 23, 2010

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Xilinx UG492 manual Standard Core Generator Format, Core Architecture