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Models: UG492

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Chapter 12: System Integration

BEGIN xps_ll_temac

PARAMETER INSTANCE = Hard_Ethernet_MAC PARAMETER C_NUM_IDELAYCTRL = 2

PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y5 PARAMETER C_FAMILY = virtex5

PARAMETER C_PHY_TYPE = 1

PARAMETER C_TEMAC1_ENABLED = 0 PARAMETER C_BUS2CORE_CLK_RATIO = 1

PARAMETER C_TEMAC_TYPE = 0 PARAMETER C_TEMAC0_PHYADDR = 0b00001 PARAMETER HW_VER = 2.02.a

PARAMETER C_TEMAC0_AVB = 1 # Enable AVB connections PARAMETER C_BASEADDR = 0x81c00000

PARAMETER C_HIGHADDR = 0x81c0ffff BUS_INTERFACE SPLB = mb_plb

BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0

PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt

PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin PORT GTX_CLK_0 = clk_125_0000MHzPLL0

PORT REFCLK = clk_200_0000MHz

PORT LlinkTemac0_CLK = clk_125_0000MHzPLL0

PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin

PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin

# Connect as per Figure 12-9

PORT Temac0AvbTxClk = Temac0AvbTxClk PORT Temac0AvbTxClkEn = Temac0AvbTxClkEn PORT Temac0AvbRxClk = Temac0AvbRxClk PORT Temac0AvbRxClkEn = Temac0AvbRxClkEn PORT Avb2Mac0TxData = Avb2Mac0TxData

PORT Avb2Mac0TxDataValid = Avb2Mac0TxDataValid

PORT Avb2Mac0TxUnderrun = Avb2Mac0TxUnderrun PORT Mac02AvbTxAck = Mac02AvbTxAck

PORT Mac02AvbRxData = Mac02AvbRxData

PORT Mac02AvbRxDataValid = Mac02AvbRxDataValid

PORT Mac02AvbRxFrameGood = Mac02AvbRxFrameGood

PORT Mac02AvbRxFrameBad = Mac02AvbRxFrameBad PORT Temac02AvbTxData = Temac02AvbTxData

PORT Temac02AvbTxDataValid = Temac02AvbTxDataValid PORT Temac02AvbTxUnderrun = Temac02AvbTxUnderrun PORT Avb2Temac0TxAck = Avb2Temac0TxAck

PORT Avb2Temac0RxData = Avb2Temac0RxData

PORT Avb2Temac0RxDataValid = Avb2Temac0RxDataValid PORT Avb2Temac0RxFrameGood = Avb2Temac0RxFrameGood PORT Avb2Temac0RxFrameBad = Avb2Temac0RxFrameBad

END

BEGIN eth_avb_endpoint

PARAMETER INSTANCE = eth_avb_endpoint_0

PARAMETER HW_VER = 2.02.a

PARAMETER C_MEM0_BASEADDR = 0xcc000000

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Ethernet AVB Endpoint User Guide

 

 

UG492 July 23, 2010

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Xilinx UG492 manual End