Example Design

Top-Level Example Design HDL

The following files describe the top-level example design for the Ethernet AVB Endpoint core.

VHDL

<project_dir>/<component_name>/example_design/<component_name>_example _design.vhd

Verilog

<project_dir>/<component_name>/example_design/<component_name>_example _design.v

The example design HDL top level contains the following:

An instance of the Ethernet AVB Endpoint core

Two instances of an Ethernet Frame Stimulus block, configured differently and connected as follows:

One instance is connected to the AV transmitter interface, configured to produce VLAN Ethernet frames with a priority of 3.

A second instance is connected to the Legacy transmitter interface, configured to produce standard Ethernet frames without a VLAN field

An instance of a Loopback Module, instantiated in place of where an Ethernet MAC should exist, enables the example design to be standalone. All AV and Legacy frames transmitted are then looped back and received at the corresponding AV and Legacy receive client interfaces.

Two instances of an Ethernet Frame Checker block, configured differently and connected as follows:

One instance is connected to the AV receiver interface, configured to expect the VLAN frames produced by the AV Frame Stimulus block

A second instance is connected to the Legacy receiver interface, configured to expect the standard Ethernet frames produced by the Legacy Frame Stimulus block

A PLB Module that connects to the PLB interface of the core and contains simple state machines to perform initialization of configuration and interrupt management state machines.

Ethernet Frame Stimulus

The following files describe the Ethernet Frame Stimulus logic:

VHDL

<project_dir>/<component_name>/example_design/tx_frame_stimulus.vhd

Verilog

<project_dir>/<component_name>/example_design/tx_frame_stimulus.v

This module contains the logic to produce an Ethernet test frame. The MAC header fields of this frame are defined by generics (Destination Address, Source Address, Length/Type); the VLAN field is optional. Additionally, the length of the Ethernet frame can also be set using a generic.

Ethernet AVB Endpoint User Guide

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UG492 July 23, 2010

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Xilinx UG492 manual Top-Level Example Design HDL, Ethernet Frame Stimulus