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Chapter 5: Core Architecture
Table
Signal | Direction | Description |
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host_miim_rdy | Input | When high, the MAC has completed its |
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| MDIO transaction |
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host_stats_lsw_rdy | Input | Signal provided by the Ethernet Statistics |
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| core to indicate that the lower |
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| the statistic counter value is present on |
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| the host_rd_data_stats[31:0] port. If the |
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| statistics core is not used, then connect to |
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| logic 0. |
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host_stats_msw_rdy | Input | Signal provided by the Ethernet Statistics |
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| core to indicate that the upper |
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| the statistic counter value is present on |
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| the host_rd_data_stats[31:0] port. If the |
|
| statistics core is not used, then connect to |
|
| logic 0. |
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|
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Processor Local Bus (PLB) Interface
The Processor Local Bus (PLB) on the Ethernet Audio Video core is designed to be integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily integrated and connected to the supported embedded processors (MicroBlaze or PowerPC). As a result, the PLB interface does not require
The PLB interface, defined by IBM, can be complex and support many usage modes (such as multiple bus masters). It can support single or burst read/writes, and can support different bus widths and different peripheral bus widths.
The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible. The following features are provided:
•
•Implements a simple PLB slave.
•Supports single read/writes only (no burst or page modes).
52 | www.xilinx.com | Ethernet AVB Endpoint User Guide |
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| UG492 July 23, 2010 |