Chapter 5: Core Architecture

Table 5-8:Tri-Mode Ethernet MAC Host Interface (Configuration/Status)

Signal

Direction

Description

 

 

 

host_miim_rdy

Input

When high, the MAC has completed its

 

 

MDIO transaction

 

 

 

host_stats_lsw_rdy

Input

Signal provided by the Ethernet Statistics

 

 

core to indicate that the lower 32-bits of

 

 

the statistic counter value is present on

 

 

the host_rd_data_stats[31:0] port. If the

 

 

statistics core is not used, then connect to

 

 

logic 0.

 

 

 

host_stats_msw_rdy

Input

Signal provided by the Ethernet Statistics

 

 

core to indicate that the upper 32-bits of

 

 

the statistic counter value is present on

 

 

the host_rd_data_stats[31:0] port. If the

 

 

statistics core is not used, then connect to

 

 

logic 0.

 

 

 

Processor Local Bus (PLB) Interface

The Processor Local Bus (PLB) on the Ethernet Audio Video core is designed to be integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily integrated and connected to the supported embedded processors (MicroBlaze or PowerPC). As a result, the PLB interface does not require in-depth understanding, and the following information is provided for reference only. See the EDK documentation for further information.

The PLB interface, defined by IBM, can be complex and support many usage modes (such as multiple bus masters). It can support single or burst read/writes, and can support different bus widths and different peripheral bus widths.

The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible. The following features are provided:

32-bit data width.

Implements a simple PLB slave.

Supports single read/writes only (no burst or page modes).

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Ethernet AVB Endpoint User Guide

 

 

UG492 July 23, 2010

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Xilinx UG492 manual Processor Local Bus PLB Interface