Error Free Legacy Frame Transmission | Xilinx UG492 specs

Chapter 6: Ethernet AVB Endpoint Transmission

Error Free Legacy Frame Transmission

tx_clk

tx_clk_enable

legacy_tx_data[7:0]

legacy_tx_data_valid

legacy_tx_ack

legacy_tx_underrun

DA

SA

L/T

DATA

Figure 6-1:Normal Frame Transmission across the Legacy Traffic Interface

Figure 6-1illustrates the timing of a normal frame transfer. When the legacy client initiates

aframe transmission, it places the first column of data onto the legacy_tx_data[7:0] port and asserts a logic 1 onto legacy_tx_data_valid. After the Ethernet AVB Endpoint core reads the first byte of data, it asserts the legacy_tx_ack signal. On the next and subsequent rising clock edges, the client must provide the remainder of the data for the frame. The end of frame is signalled to the core by taking the legacy_tx_data_valid to logic 0.

58	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

Image 58

Xilinx UG492 manual Error Free Legacy Frame Transmission, Ethernet AVB Endpoint Transmission

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23 Revision History Date Version Revision Table of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home Network Constraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This Guide Conventions Typographical Conventions Online DocumentConvention Meaning or Use Example List of Abbreviations Acronym Spelled Out Conventions Acronym Spelled Out Vhdl Preface About This Guide About the Core IntroductionSystem Requirements Windows Technical Support Recommended Design ExperienceAdditional Core Resources Feedback Document Feedback Introduction Simulation Only Licensing the CoreBefore you Begin License Options Full System Hardware Evaluation Installing the License File Obtaining Your License Key Overview of Ethernet Audio Video Bridging 1Example AVB Home Network P802.1AS AVB SpecificationsOverview of Ethernet Audio Video Bridging Talker Assumptions AVB SpecificationsP802.1Qav Listener Assumptions Typical Implementation P802.1Qat Typical Implementation UG492 July 23 Generating the Core Ethernet AVB GUI Core Delivery Format Component NameGenerating the Core PLB Base Address Number of PLB MastersEthernet AVB GUI Parameter Values in the XCO File Output Generation Core Architecture Standard Core Generator Format Core Architecture EDK pcore Format EDK pcore Format AV Traffic Interface Functional Block DescriptionPLB Interface Legacy Traffic Interface MAC Header Filters Tx ArbiterRx Splitter Functional Block Description Tx Time Stamp Precise Timing Protocol BlocksTx PTP Packet Buffers Rx PTP Packet Buffers RTC Software Drivers Tri-Mode Ethernet MACs Core Interfaces Clocks and Reset1Clocks and Resets Signal Direction Description Core Interfaces Legacy Traffic Receiver Path Signals Legacy Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path Direction Description 3Legacy Traffic Signals Receiver Path AV Traffic Transmitter Path Signals4AV Traffic Signals Transmitter Path Direction Description Tri-Mode Ethernet MAC Client Interface AV Traffic Receiver Path Signals5AV Traffic Signals Receiver Path Direction Description MAC Transmitter Interface MAC Receiver Interface MAC Management Interface Processor Local Bus PLB Interface PLB Interface PIN Name Direction Description Ethernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction Description PTP Signals Signal Direction Description Ethernet AVB Endpoint Transmission Tx Legacy Traffic I/F Error Free Legacy Frame Transmission Ethernet AVB Endpoint Transmission Tx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Credit Based Traffic Shaping Algorithm Tx ArbiterOverview Tx Arbiter 4Credit-based Shaper Operation IdleSlope Tx Arbiter Bandwidth ControlSendSlope HiLimit LoLimit Rx Splitter Ethernet AVB Endpoint ReceptionRx Legacy Traffic I/F Error Free Legacy Frame Reception Ethernet AVB Endpoint Reception Overview of Operation Errored Legacy Frame ReceptionLegacy MAC Header Filters Rx Legacy Traffic I/F 3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA Match Partial Destination Address DA Match 5Filtering of Frames with a Partial DA Match Vlan Priority Match Any Other Combinations Rx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic Interface Real Time Clock and Time Stamping Real Time Clock Real Time Clock and Time Stamping Increment of Nanoseconds Field RTC ImplementationReal Time Clock Controlled Frequency RTC Increment of the Seconds FieldSynchronized RTC Time Stamping Logic Time Stamping Logic Time Stamp Sampling Position of MAC Frames 3Time Stamping Position IEEE1722 Real Time Clock Format IEEE1722 Real Time Clock Format Real Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer Structure Rx PTP Packet Buffer Rx PTP Packet Buffer 2Rx PTP Packet Buffer Processor Local Bus Interface Configuration and StatusSingle Read Transaction Configuration and Status 1Single Read Transaction Single Write Transaction Processor Local Bus Interface PLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space Rx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration RegistersEthernet AVB Endpoint Address Space Tx PTP Packet Buffer Address Space Rx PTP Packet Control Register Rx Filtering Control Register Tx Arbiter Idle Slope Control Register Tx Arbiter Send Slope Control RegisterRTC Offset Control Registers RTC Increment Value Control Register Current RTC Value Registers RTC Interrupt Clear Register Software Reset Register Phase Adjustment Register PTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access Description Tri-Mode Ethernet MAC Address Space MAC Configuration and StatisticsMAC Address Filter Registers MAC Mdio Registers 102 Constraining the Core Required Constraints Hostclk Period Constraints for Clock NetsPLBclk Txclk Rtcclk Timespecs for Critical Logic within the CoreRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System Integration Tri-Mode Ethernet MAC Core Generation LogiCORE IP Tri-Mode Ethernet MAC Soft CoreSystem Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics 114 Connections Including Ethernet Statistics GND LogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLB Using an ISE Software Top-Level Project PLB Ethernet AVB Endpoint User Guide 123 Xpslltemac configuration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACIntroduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemac Ethernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC END Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock Master Driver Instantiation Clock SlaveSoftware System Integration Software Drivers Interrupt Service Routine Connections Software System Integration Core Initialization Ethernet AVB Endpoint SetupWhen Using a LogiCORE IP Tri-Mode Ethernet MAC System-Specific Defines in xavbhw.h Setting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback Handler Starting and Stopping the AVB Drivers Quick Start Example Design Overview Quick Start Example Design 1Ethernet AVB Endpoint Example Design and Test Bench Generating the Core 2Ethernet AVB Endpoint Core Customization Screen Simulating the Example Design Setting up for Simulation Functional SimulationImplementing the Example Design Implementing the Example Design What’s Next? Timing Simulation Detailed Example Design Standard Format Project directory Directory and File Contents Component name/doc Project directory/component nameComponent name/example design Component name/implement 5Implement Directory Name Description Simulation/functional Implement/resultsComponent name/simulation 6Results Directory Name Description Simulation/timing Name Description Drivers/avbv204a/examples Componentname/drivers/v204aDrivers/avbv204a/data 11Driver Example Directory Name Description Drivers/avbv204a/src Simulation Scripts Implementation ScriptsImplementation Scripts Example Design Example Design HDL for the Ethernet AVB Endpoint Ethernet Frame Stimulus Top-Level Example Design HDLExample Design Ethernet Frame Checker Loopback Module PLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test Bench Simulation Run Time Customizing the Test BenchChanging Frame Data 3Simulator Wave Window Contents Viewing the Simulation Wave Form Detailed Example Design EDK format Detailed Example Design EDK format MyProcessorIPLib/pcores/ethavbendpointv204a Component name/MyProcessorIPLibPcores/ethavbendpointv204a/data MyProcessorIPLib/drivers/avbv204a Pcores/ethavbendpointv204a/hdl/vhdlPcores/ethavbendpointv204a/netlist 5Driver Data Directory Name Description 8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Time Stamp Accuracy RTC Real Time Instantaneous ErrorTime Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp Accuracy RTC Sampling Error Time Stamp Accuracy Figure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy 172