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Chapter 10: Configuration and Status
Ethernet AVB Endpoint Address Space
Rx PTP Packet Buffer Address Space
The Address space of the “Rx PTP Packet Buffer” is 4k bytes, from PLB_base_address to (PLB_base_address + 0x0FFF). This represents the size of a single
Tx PTP Packet Buffer Address Space
The Address space of the “Tx PTP Packet Buffer” is continuous from (PLB_base_address + 0x1000) to (PLB_base_address + 0x17FF), representing the size of a single
Ethernet Audio Video End Point Configuration Registers
Tx PTP Packet Control Register
Table
Table
Bit no | Default | Access | Description |
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0 | WO | tx_send_frame bits. The Tx PTP Packet Buffer is split into | |
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| 8 regions of 256 bytes. Each of these can contain a separate |
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| PTP frame. There is 1 tx_send_frame bit for each of the 8 |
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| regions. |
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| Each bit, when written to ‘1’, will cause a request to be |
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| made to the “Tx Arbiter.” When access is granted, the |
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| frame contained within the respected region will be |
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| transmitted. |
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| If read, will always return 0. |
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0 | RO | tx_frame_waiting indication. The Tx PTP Packet Buffer is | |
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| split into 8 regions of 256 bytes, each of which can contain |
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| a separate PTP frame. There is 1 tx_frame_waiting bit for |
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| each of the 8 regions. |
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| Each bit, when logic 1, indicates that a request has been |
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| made for frame transmission to the “Tx Arbiter,” but that |
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| a grant has not yet occurred. When the frame has been |
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| successfully transmitted, the bit will be set to logic 0. |
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| This bit allows the microprocessor to run off a polling |
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| implementation as opposed to the Interrupts. |
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0 | RO | tx_packet. indicates the number (block RAM bin position) | |
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| of the most recently transmitted PTP packet. |
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0 | RO | Unused | |
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Note: A read or a write to this register clears the interrupt_ptp_tx interrupt (asserted after each successful PTP packet transmission).
92 | www.xilinx.com | Ethernet AVB Endpoint User Guide |
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| UG492 July 23, 2010 |