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Xilinx UG492 Configuration and Status, Processor Local Bus Interface, Single Read Transaction

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Chapter 10

Configuration and Status

This chapter provides general guidelines for configuring and monitoring the Ethernet AVB Endpoint core, including an introduction to the PLB configuration bus and a description of the core management registers.

Processor Local Bus Interface

The Processor Local Bus (PLB) bus on the Ethernet AVB Endpoint core is designed to be integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily integrated and connected to the supported embedded processors (MicroBlaze™ or PowerPC®). As a result, the PLB interface does not require in-depth understanding and the following information is provided for reference only. See the EDK documentation for further information.

The PLB interface, defined by IBM, can be complex and support many usage modes (such as multiple bus masters). It can support single or burst read/writes, and can support different bus widths and different peripheral bus widths.

The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible. The following features are provided:

•32-bit data width.

•Implements a simple PLB slave.

•Supports single read/writes only (no burst or page modes).

Single Read Transaction

Figure 10-1illustrates a single read data transfer on the PLB. Note the following:

•Wait states can be added to the Address cycle by asserting Sl_wait and delaying

Sl_addrAck.

•Wait states can be inserted in the Read fetch by delaying the assertion of Sl_rdDAck.

Ethernet AVB Endpoint User Guide

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UG492 July 23, 2010

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Xilinx UG492 manual Configuration and Status, Processor Local Bus Interface, Single Read Transaction

Contents

UG492 July 23 LogiCORETM IP Ethernet AVB EndpointDate Version Revision Revision HistoryTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide 1Example AVB Home Network Schedule of FiguresConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide About This Guide Guide ContentsTypographical ConventionsOnline Document ConventionsConvention Meaning or Use Example Acronym Spelled Out List of AbbreviationsVhdl Conventions Acronym Spelled OutPreface About This Guide Windows IntroductionSystem Requirements About the CoreFeedback Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback DocumentIntroduction Full System Hardware Evaluation Licensing the CoreBefore you Begin License Options Simulation OnlyObtaining Your License Key Installing the License File1Example AVB Home Network Overview of Ethernet Audio Video BridgingAVB Specifications P802.1ASOverview of Ethernet Audio Video Bridging Listener Assumptions AVB SpecificationsP802.1Qav Talker AssumptionsP802.1Qat Typical ImplementationTypical Implementation UG492 July 23 Ethernet AVB GUI Generating the CoreComponent Name Core Delivery FormatGenerating the Core Number of PLB Masters PLB Base AddressEthernet AVB GUI Output Generation Parameter Values in the XCO FileCore Architecture Core Architecture Standard Core Generator FormatEDK pcore Format EDK pcore FormatLegacy Traffic Interface Functional Block DescriptionPLB Interface AV Traffic InterfaceFunctional Block Description Tx ArbiterRx Splitter MAC Header FiltersRx PTP Packet Buffers Precise Timing Protocol BlocksTx PTP Packet Buffers Tx Time StampRTC Tri-Mode Ethernet MACs Software DriversCore Interfaces Clocks and Reset1Clocks and Resets Signal Direction Description Core InterfacesLegacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals3Legacy Traffic Signals Receiver Path Direction Description AV Traffic Transmitter Path Signals 3Legacy Traffic Signals Receiver Path4AV Traffic Signals Transmitter Path Direction Description MAC Transmitter Interface AV Traffic Receiver Path Signals5AV Traffic Signals Receiver Path Direction Description Tri-Mode Ethernet MAC Client InterfaceMAC Management Interface MAC Receiver InterfaceProcessor Local Bus PLB Interface PIN Name Direction Description PLB InterfaceEthernet AVB Endpoint User Guide 10Interrupt Signals Direction Description Interrupt SignalsSignal Direction Description PTP SignalsTx Legacy Traffic I/F Ethernet AVB Endpoint TransmissionEthernet AVB Endpoint Transmission Error Free Legacy Frame TransmissionErrored Legacy Frame Transmission Tx AV Traffic I/FTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Tx Arbiter Tx ArbiterOverview Credit Based Traffic Shaping Algorithm4Credit-based Shaper Operation Tx Arbiter Bandwidth Control IdleSlopeSendSlope LoLimit HiLimitEthernet AVB Endpoint Reception Rx SplitterRx Legacy Traffic I/F Ethernet AVB Endpoint Reception Error Free Legacy Frame ReceptionRx Legacy Traffic I/F Errored Legacy Frame ReceptionLegacy MAC Header Filters Overview of Operation3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Full Destination Address DA Match Single MAC Header Filter Usage Examples5Filtering of Frames with a Partial DA Match Partial Destination Address DA MatchAny Other Combinations Vlan Priority MatchError Free AV Traffic Reception Rx AV Traffic I/FRx AV Traffic I/F 8Errored Frame Reception across the AV Traffic Interface Errored AV Traffic ReceptionReal Time Clock Real Time Clock and Time StampingReal Time Clock and Time Stamping RTC Implementation Increment of Nanoseconds FieldReal Time Clock Increment of the Seconds Field Controlled Frequency RTCSynchronized RTC Time Stamping Logic Time Stamping Logic3Time Stamping Position Time Stamp Sampling Position of MAC FramesIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers1Tx PTP Packet Buffer Structure Precise Timing Protocol Packet BuffersRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Configuration and Status Processor Local Bus InterfaceSingle Read Transaction 1Single Read Transaction Configuration and StatusProcessor Local Bus Interface Single Write TransactionPLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space PLB Address Map and Register DefinitionsTx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration RegistersEthernet AVB Endpoint Address Space Rx PTP Packet Buffer Address SpaceRx Filtering Control Register Rx PTP Packet Control RegisterTx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control RegisterRTC Offset Control Registers Current RTC Value Registers RTC Increment Value Control RegisterRTC Interrupt Clear Register Phase Adjustment Register Software Reset RegisterPTP Receiver logic reset. When written with a Address Default Access Description 16MAC Header Filter Configuration Registers Cont’dMAC Configuration and Statistics Tri-Mode Ethernet MAC Address SpaceMAC Address Filter Registers MAC Mdio Registers 102 Required Constraints Constraining the CoreTxclk Period Constraints for Clock NetsPLBclk HostclkTimespecs for Critical Logic within the Core RtcclkRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACsLogiCORE IP Tri-Mode Ethernet MAC Soft Core Tri-Mode Ethernet MAC Core GenerationSystem Integration Connections Without Ethernet Statistics Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs114 GND Connections Including Ethernet StatisticsLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 PLB Using an EDK Project Top LevelPLB Using an ISE Software Top-Level ProjectEthernet AVB Endpoint User Guide 123 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Xpslltemac configurationIntroduction System Overview AVB capable xpslltemac Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACEthernet AVB Endpoint Connections 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC MHS File SyntaxEND Ethernet AVB Endpoint User Guide 129 130 Clock Master Software DriversSoftware Drivers Clock SlaveSoftware System Integration Driver InstantiationSoftware System Integration Interrupt Service Routine ConnectionsSystem-Specific Defines in xavbhw.h Ethernet AVB Endpoint SetupWhen Using a LogiCORE IP Tri-Mode Ethernet MAC Core InitializationSetting up GrandMaster Discontinuity Callback Handler Setting up SourcePortIdentity and Default TX PTP MessagesStarting and Stopping the AVB Drivers Overview Quick Start Example Design1Ethernet AVB Endpoint Example Design and Test Bench Quick Start Example DesignGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Implementing the Example Design Setting up for Simulation Functional SimulationImplementing the Example Design Simulating the Example DesignTiming Simulation What’s Next?Project directory Detailed Example Design Standard FormatDirectory and File Contents Project directory/component name Component name/docComponent name/example design 5Implement Directory Name Description Component name/implement6Results Directory Name Description Implement/resultsComponent name/simulation Simulation/functionalName Description Simulation/timing11Driver Example Directory Name Description Componentname/drivers/v204aDrivers/avbv204a/data Drivers/avbv204a/examplesDrivers/avbv204a/src Implementation Scripts Simulation ScriptsImplementation Scripts Example Design HDL for the Ethernet AVB Endpoint Example DesignTop-Level Example Design HDL Ethernet Frame StimulusExample Design Loopback Module Ethernet Frame CheckerPLB Module 2Ethernet AVB Endpoint Demonstration Test Bench Demonstration Test BenchCustomizing the Test Bench Simulation Run TimeChanging Frame Data Viewing the Simulation Wave Form 3Simulator Wave Window ContentsDetailed Example Design EDK format Detailed Example Design EDK format Component name/MyProcessorIPLib MyProcessorIPLib/pcores/ethavbendpointv204aPcores/ethavbendpointv204a/data 5Driver Data Directory Name Description Pcores/ethavbendpointv204a/hdl/vhdlPcores/ethavbendpointv204a/netlist MyProcessorIPLib/drivers/avbv204a8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Real Time Instantaneous Error RTC Time Stamp AccuracyTime Stamp Accuracy Appendix a RTC Time Stamp Accuracy Figure A-1RTC Periodic ErrorTime Stamp Accuracy RTC Sampling ErrorFigure A-3Sampling Position Uncertainty Figure A-4Overall Time Stamp Accuracy Accuracy Resulting from the Combined Errors172