Single Write Transaction | Xilinx UG492 guide

Processor Local Bus Interface

Single Write Transaction

Figure 10-2illustrates a single write data transfer on the PLB. Note the following:

•Wait states can be added to the Address cycle by asserting Sl_wait and delaying

Sl_addrAck.

•Wait states can be inserted in the Write sample by delaying the assertion of

Sl_wrDAck.

PLB_clk

PLB_RNW

PLB_BE[0:7]11111111

PLB_size[0:3]0000

PLB_type[0:2]000

PLB_abort

PLB_ABus[0:31]A0

PLB_AValid

SI_wait

SI_addrAck

PLB_wrDBus[0:31]D(A0)

SI_wrDAck

SI_wrComp

PLB_wrBurst

SI_rdDBus[0:31] 0000

SI_rdWrAddr[0:3] 0000

SI_rdDAck

SI_rdComp

PLB_rdBurst

Figure 10-2:Single Write Transaction

Ethernet AVB Endpoint User Guide

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UG492 July 23, 2010

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Xilinx UG492 manual Single Write Transaction, Processor Local Bus Interface

Contents

UG492 July 23 LogiCORETM IP Ethernet AVB Endpoint Date Version Revision Revision History Table of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide 1Example AVB Home Network Schedule of Figures Constraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide About This Guide Guide Contents Typographical Conventions Convention Meaning or Use Example Online DocumentConventions Acronym Spelled Out List of Abbreviations Vhdl Conventions Acronym Spelled Out Preface About This Guide System Requirements IntroductionAbout the Core Windows Additional Core Resources Recommended Design ExperienceTechnical Support Feedback Feedback Document Introduction Before you Begin License Options Licensing the CoreSimulation Only Full System Hardware Evaluation Obtaining Your License Key Installing the License File 1Example AVB Home Network Overview of Ethernet Audio Video Bridging Overview of Ethernet Audio Video Bridging AVB SpecificationsP802.1AS P802.1Qav AVB SpecificationsTalker Assumptions Listener Assumptions P802.1Qat Typical Implementation Typical Implementation UG492 July 23 Ethernet AVB GUI Generating the Core Generating the Core Component NameCore Delivery Format Ethernet AVB GUI Number of PLB MastersPLB Base Address Output Generation Parameter Values in the XCO File Core Architecture Core Architecture Standard Core Generator Format EDK pcore Format EDK pcore Format PLB Interface Functional Block DescriptionAV Traffic Interface Legacy Traffic Interface Rx Splitter Tx ArbiterMAC Header Filters Functional Block Description Tx PTP Packet Buffers Precise Timing Protocol BlocksTx Time Stamp Rx PTP Packet Buffers RTC Tri-Mode Ethernet MACs Software Drivers 1Clocks and Resets Signal Direction Description Clocks and ResetCore Interfaces Core Interfaces 3Legacy Traffic Signals Receiver Path Direction Description Legacy Traffic Transmitter Path SignalsLegacy Traffic Receiver Path Signals 4AV Traffic Signals Transmitter Path Direction Description AV Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path 5AV Traffic Signals Receiver Path Direction Description AV Traffic Receiver Path SignalsTri-Mode Ethernet MAC Client Interface MAC Transmitter Interface MAC Management Interface MAC Receiver Interface Processor Local Bus PLB Interface PIN Name Direction Description PLB Interface Ethernet AVB Endpoint User Guide 10Interrupt Signals Direction Description Interrupt Signals Signal Direction Description PTP Signals Tx Legacy Traffic I/F Ethernet AVB Endpoint Transmission Ethernet AVB Endpoint Transmission Error Free Legacy Frame Transmission Tx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Overview Tx ArbiterCredit Based Traffic Shaping Algorithm Tx Arbiter 4Credit-based Shaper Operation SendSlope Tx Arbiter Bandwidth ControlIdleSlope LoLimit HiLimit Rx Legacy Traffic I/F Ethernet AVB Endpoint ReceptionRx Splitter Ethernet AVB Endpoint Reception Error Free Legacy Frame Reception Legacy MAC Header Filters Errored Legacy Frame ReceptionOverview of Operation Rx Legacy Traffic I/F 3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Full Destination Address DA Match Single MAC Header Filter Usage Examples 5Filtering of Frames with a Partial DA Match Partial Destination Address DA Match Any Other Combinations Vlan Priority Match Rx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F 8Errored Frame Reception across the AV Traffic Interface Errored AV Traffic Reception Real Time Clock Real Time Clock and Time Stamping Real Time Clock and Time Stamping Real Time Clock RTC ImplementationIncrement of Nanoseconds Field Synchronized RTC Increment of the Seconds FieldControlled Frequency RTC Time Stamping Logic Time Stamping Logic 3Time Stamping Position Time Stamp Sampling Position of MAC Frames IEEE1722 Real Time Clock Format IEEE1722 Real Time Clock Format Real Time Clock and Time Stamping Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer Structure Precise Timing Protocol Packet Buffers Rx PTP Packet Buffer Rx PTP Packet Buffer 2Rx PTP Packet Buffer Single Read Transaction Configuration and StatusProcessor Local Bus Interface 1Single Read Transaction Configuration and Status Processor Local Bus Interface Single Write Transaction PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space Ethernet Audio Video End Point Configuration RegistersRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address Space Rx Filtering Control Register Rx PTP Packet Control Register RTC Offset Control Registers Tx Arbiter Send Slope Control RegisterTx Arbiter Idle Slope Control Register Current RTC Value Registers RTC Increment Value Control Register RTC Interrupt Clear Register Phase Adjustment Register Software Reset Register PTP Receiver logic reset. When written with a Address Default Access Description 16MAC Header Filter Configuration Registers Cont’d MAC Address Filter Registers MAC Configuration and StatisticsTri-Mode Ethernet MAC Address Space MAC Mdio Registers 102 Required Constraints Constraining the Core PLBclk Period Constraints for Clock NetsHostclk Txclk Required Constraints Timespecs for Critical Logic within the CoreRtcclk Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System Integration LogiCORE IP Tri-Mode Ethernet MAC Soft CoreTri-Mode Ethernet MAC Core Generation Connections Without Ethernet Statistics Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs 114 GND Connections Including Ethernet Statistics LogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 PLB Using an EDK Project Top Level PLB Using an ISE Software Top-Level Project Ethernet AVB Endpoint User Guide 123 Introduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACXpslltemac configuration System Overview AVB capable xpslltemac Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Ethernet AVB Endpoint Connections 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC MHS File Syntax END Ethernet AVB Endpoint User Guide 129 130 Clock Master Software Drivers Software System Integration Clock SlaveDriver Instantiation Software Drivers Software System Integration Interrupt Service Routine Connections When Using a LogiCORE IP Tri-Mode Ethernet MAC Ethernet AVB Endpoint SetupCore Initialization System-Specific Defines in xavbhw.h Setting up GrandMaster Discontinuity Callback Handler Setting up SourcePortIdentity and Default TX PTP Messages Starting and Stopping the AVB Drivers Overview Quick Start Example Design 1Ethernet AVB Endpoint Example Design and Test Bench Quick Start Example Design Generating the Core 2Ethernet AVB Endpoint Core Customization Screen Implementing the Example Design Setting up for Simulation Functional SimulationSimulating the Example Design Implementing the Example Design Timing Simulation What’s Next? Project directory Detailed Example Design Standard Format Directory and File Contents Component name/example design Project directory/component nameComponent name/doc 5Implement Directory Name Description Component name/implement Component name/simulation Implement/resultsSimulation/functional 6Results Directory Name Description Name Description Simulation/timing Drivers/avbv204a/data Componentname/drivers/v204aDrivers/avbv204a/examples 11Driver Example Directory Name Description Drivers/avbv204a/src Implementation Scripts Implementation ScriptsSimulation Scripts Example Design HDL for the Ethernet AVB Endpoint Example Design Example Design Top-Level Example Design HDLEthernet Frame Stimulus Loopback Module Ethernet Frame Checker PLB Module 2Ethernet AVB Endpoint Demonstration Test Bench Demonstration Test Bench Changing Frame Data Customizing the Test BenchSimulation Run Time Viewing the Simulation Wave Form 3Simulator Wave Window Contents Detailed Example Design EDK format Detailed Example Design EDK format Pcores/ethavbendpointv204a/data Component name/MyProcessorIPLibMyProcessorIPLib/pcores/ethavbendpointv204a Pcores/ethavbendpointv204a/netlist Pcores/ethavbendpointv204a/hdl/vhdlMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description 8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 Time Stamp Accuracy RTC Real Time Instantaneous ErrorRTC Time Stamp Accuracy Appendix a RTC Time Stamp Accuracy Figure A-1RTC Periodic Error Time Stamp Accuracy RTC Sampling Error Figure A-3Sampling Position Uncertainty Figure A-4Overall Time Stamp Accuracy Accuracy Resulting from the Combined Errors 172