Chapter 5: Core Architecture

Table 5-9:PLB Signals (Cont’d)

PIN Name

Direction

Description

 

 

 

PLB_wrPendPri[0:1]

Input

Unused. PLB pending read bus request

 

 

indicator.

 

 

 

PLB_reqPri[0:1]

Input

Unused. PLB request priority.

 

 

 

Sl_addrAck

Output

Slave address acknowledge

 

 

 

Sl_SSize[0:1]

Output

Slave data bus size.

 

 

 

Sl_wait

Output

Slave wait indicator.

 

 

 

Sl_rearbitrate

Output

Slave rearbitrate bus indicator. Not used,

 

 

tied to logic 0.

 

 

 

Sl_wrDack

Output

Slave write data acknowledge

 

 

 

Sl_wrComp

Output

Slave write transfer complete indicator

 

 

 

Sl_WrBTerm

Output

Slave terminate write burst transfer.

 

 

 

Sl_rdBus[0:31]

Output

Slave read data bus

 

 

 

Sl_rdWdAddr[0:3]

Output

Slave read word address

 

 

 

Sl_rdDAck

Output

Slave read data acknowledge

 

 

 

Sl_rdComp

Output

Slave read transfer complete indicator

 

 

 

Sl_rdBTerm

Output

Slave terminate read burst transfer.

 

 

 

Sl_MBusy[0:NUM_MASTERS-1]

Output

Slave busy indicator

 

 

 

Sl_MWrErr[0:NUM_MASTERS-1]

Output

Unused, tied to logic 0. Slave write error

 

 

indicator.

 

 

 

Sl_MRdErr[0:NUM_MASTERS-1]

Output

Unused, tied to logic 0. Slave read error

 

 

indicator.

 

 

 

Sl_MIRQ[0:NUM_MASTERS-1]

Output

Unused, tied to logic 0. Slave interrupt

 

 

indicator.

 

 

 

54

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Ethernet AVB Endpoint User Guide

 

 

UG492 July 23, 2010

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Xilinx UG492 manual Ethernet AVB Endpoint User Guide