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Xilinx UG492 Recommended Design Experience, Additional Core Resources, Technical Support, Feedback

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24 www.xilinx.com Ethernet AVB Endpoint User Guide

UG492 July 23, 2010

Chapter 1: Introduction

Recommended Design Experience

Although the Ethernet AVB Endpoint core is a fully verified solution, the challenge

associated with implementing a complete design varies depending on the configuration

and functionality of the application. For best results, previous experience building high-

performance, pipelined FPGA designs using Xilinx implementation software and user

constraint files (UCFs) is recommended. In addition, previous experience using the

Embedded Development Kit (EDK) and developing embedded software applications is

recommended. Contact your local Xilinx representative for a closer review and estimation

for your specific requirements.

Additional Core Resources

For detailed information and updates about the Ethernet AVB Endpoint core, see the

following documents, available from the product page.

•Ethernet AVB Endpoint Data Sheet

•Ethernet AVB Endpoint User Guide

From the document directory after generating the core:

•Ethernet AVB Endpoint Release Notes

Technical Support

For technical support, see www.support.xilinx.com/. Questions are routed to a team of

engineers with expertise using the Ethernet AVB Endpoint core.

Xilinx provides technical support for use of this product as described in this guide. Xilinx

cannot guarantee timing, functionality, or support of this product for designs that do not

follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the Ethernet AVB Endpoint core and

the documentation supplied with the core.

Ethernet AVB Endpoint Core

For comments or suggestions about the Ethernet AVB Endpoint core, submit a WebCase

from www.xilinx.com/support/clearexpress/websupport.htm/

Be sure to include the following information:

•Product name

•Core version number

•Explanation of your comments

Contents

Main Revision History The following table shows the revision history for this document. Table of Contents Schedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Chapter 4: Generating the Core Chapter 5: Core Architecture Chapter 6: Ethernet AVB Endpoint Transmission Chapter 7: Ethernet AVB Endpoint Reception Chapter 8: Real Time Clock and Time Stamping Chapter 9: Precise Timing Protocol Packet Buffers Chapter 10: Configuration and Status Chapter 11: Constraining the Core Chapter 12: System Integration Chapter 14: Quick Start Example Design Chapter 15: Detailed Example Design (Standard Format) Chapter 16: Detailed Example Design (EDK format) Directory and File Contents Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit (EDK) Appendix A: RTC Time Stamp Accuracy Time Stamp Accuracy Page Schedule of Figures Page Page Page Schedule of Tables Page Page Page Preface About This Guide Guide Contents Conventions Typographical Conventions Online Document The following conventions are used in this document: Preface: About This Guide List of Abbreviations The following table describes acronyms used in this manual. Page Page Chapter 1 Introduction System Requirements Windows Software About the Core Recommended Design Experience Additional Core Resources Technical Support Feedback Ethernet AVB Endpoint Core Document Page Chapter 2 Licensing the Core Before you Begin License Options Simulation Only Full System Hardware Evaluation Obtaining Your License Key Simulation License Full System Hardware Evaluation License Obtaining a Full License Key Installing the License File Overview of Ethernet Audio Video Bridging AVB Specifications P802.1AS P802.1Qav Tal k e r Assumptions Listener Assumptions P802.1Qat Typical Implementation Page Page Chapter 4 Generating the Core Ethernet AVB GUI Page 1 Component Name Core Delivery Format Ethernet AVB GUI Page 2 Number of PLB Masters PLB Base Address Parameter Values in the XCO File Output Generation Chapter 5 Core Architecture Standard CORE Generator Format EDK pcore Format Functional Block Description PLB Interface AV Traffic Interface Legacy Traffic Interface Tx Arbiter Rx Splitter MAC Header Filters Precise Timing Protocol Blocks Tx PTP Packet Buffers Tx Time Stamp Rx PTP Packet Buffers Rx Time Stamp RTC Software Drivers Tri-Mode Ethernet MACs Core Interfaces Clocks and Reset Legacy Traffic Interface Legacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals Core Interfaces AV Traffic Interface AV Traffic Transmitter Path Signals Table 5-3: Legacy Traffic Signals: Receiver Path Table 5-4: AV Traffic Signals: Transmitter Path AV Traffic Receiver Path Signals Tri-Mode Ethernet MAC Client Interface MAC Transmitter Interface MAC Receiver Interface MAC Management Interface Processor Local Bus (PLB) Interface Core Interfaces PLB Interface Chapter 5: Core Architecture Table 5-9: PLB Signals (Contd) Interrupt Signals PTP Signals Chapter 6 Ethernet AVB Endpoint Transmission Tx Legacy Traffic I/F Error Free Legacy Frame Transmission Errored Legacy Frame Transmission Tx AV Traffic I/F Page Tx Arbiter Overview Credit Based Traffic Shaping Algorithm Page Tx Arbiter Bandwidth Control idleSlope sendSlope hiLimit loLimit Chapter 7 Ethernet AVB Endpoint Reception Rx Splitter Rx Legacy Traffic I/F Error Free Legacy Frame R ecepti on Errored Legacy Frame Reception Legacy MAC Header Filters Overview of Operation Page MAC Header Filter Configuration Chapter 7: Ethernet AVB Endpoint Reception Single MAC Header Filter Usage Examples Figure 7-4: Filtering of Frames with a Full DA Match Full Destination Address (DA) Match rx_clk legacy_rx_data[7:0] legacy_rx_data_valid Partial Destination Address (DA) Match Figure 7-5: Filtering of Frames with a Partial DA Match rx_clk legacy_rx_data[7:0] legacy_rx_data_valid rx_clk_enable DA SA DATAL/T VLAN Priority Match Any Other Combinations Rx AV Traffic I/F Error Free AV Traffic Reception Errored AV Traffic Reception Chapter 8 Real Time Clock and Time Stamping Real Time Clock Page RTC Implementation Increment of Nanoseconds Field (Step 1) Controlled Frequency RTC (Step 2) Synchronized RTC Increment of the Seconds Field Clock Outputs Based on the Synchronized RTC Nanoseconds Field Time Stamping Logic Time Stamp Sampling Position of MAC Frames IEEE1722 Real Time Clock Format Page Chapter 9 Precise Timing Protocol Packet Buffers Tx PTP Packet Buffer Page Rx PTP Packet Buffer Figure 9-2: Rx PTP Packet Buffer Chapter 10 Configuration and Status Processor Local Bus Interface Single Read Transaction Chapter 10: Configuration and Status Figure 10-1: Single Read Transaction Single Write Transaction PLB Address Map and Register Definitions Page Ethernet AVB Endpoint Address Space Rx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration Registers Tx PTP Packet Control Register Rx PTP Packet Control Register Rx Filtering Control Register Tx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control Register RTC Offset Control Registers RTC Increment Value Control Register Current RTC Value Registers RTC Interrupt Clear Register Phase Adjustment Register Software Reset Register MAC Header Filter Configuration PLB Address Map and Register Definitions Table 10-16: MAC Header Filter Configuration Registers (Contd) Tri-Mode Ethernet MAC Address Space MAC Configuration and Statistics MAC Address Filter Registers MAC MDIO Registers Page Chapter 11 Constraining the Core Required Constraints Device, Package, and Speedgrade Selection I/O Location Constraints Placement Constraints PERIOD Constraints for Clock Nets PLB_clk host_clk tx_clk rx_clk Timespecs for Critical Logic within the Core Page Page Page Required Constraints Page Chapter 12 System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs LogiCORE IP Tri-Mode Ethernet MAC (Soft Core) Tri-Mode Ethernet MAC Core Generation Connections Without Ethernet Statistics Figure 12-1: Connection to the Tri-Mode Ethernet MAC Core (without Ethernet Statistics) Page Ethernet AVB Endpoint User Guide www.xilinx.com 115 Connections Including Ethernet Statistics Figure 12-2: Connection to the Tri-Mode Ethernet MAC and Ethernet Statistic Cores the host_rd_data[31:0] port of the Ethernet Statistics core. connect host_rd_data_mac[31:0] of the Ethernet AVB Endpoint core to the host_rd_data[31:0] port of the TEMAC. LogiCORE IP Embedded Tri-Mode Ethernet MACs Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper Generation Connections Without Ethernet Statistics Connections Including Ethernet Statistics host_clk CLIENTEMAC0PAUSEREQ CLIENTEMAC0PAUSEVAL[15:0] EMAC0CLIENTTXSTATS EMAC0CLIENTTXSTATSVLD EMAC0CLIENTTXSTATSBYTEVLD EMAC0CLIENTRXSTATS[6:0] EMAC0CLIENTRXSTATSVLD EMAC0CLIENTRXSTATSBYTEVLD Connection of the PLB to the EDK for LogiCORE IP Ethernet MACs Figure 12-5: Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub-system Using an EDK Project Top Level Using an ISE Software Top-Level Project t Figure 12-7: Connection into an Embedded Processor Sub-system with an ISE Software Top-Level Project Page Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Introduction xps_ll_temac configuration System Overview: AVB capable xps_ll_temac t Figure 12-8: Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub-system Ethernet AVB Endpoint Connections MHS File Syntax Figure 12-9: Connection to the XPS LocalLink Tri-Mode Ethernet MAC Page Page Page Chapter 13 Software Drivers Clock Master Clock Slave Software System Integration Driver Instantiation Interrupt Service Routine Connections Core Initialization When Using a LogiCORE IP Tri-Mode Ethernet MAC Ethernet AVB Endpoint Setup System-Specific Defines in xavb_hw.h System-Specific Defines in xavb.h Setting up SourcePortIdentity (and Default TX PTP Messages) Setting up GrandMaster Discontinuity Callback Handler Starting and Stopping the AVB Drivers Chapter 14 Quick Start Example Design Overview Figure 14-1: Ethernet AVB Endpoint Example Design and Test Bench Generating the Core Page Implementing the Example Design Simulating the Example Design Setting up for Simulation Functional Simulation Timing Simulation Whats Next? Chapter 15 Detailed Example Design (Standard Format) Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/example design <component name>/implement The implement directory contains the core implementation script files. Table 15-4: Example Design Directory (Contd) Table 15-5: Implement Directory implement/results <component name>/simulation simulation/functional simulation/timing The timing directory contains timing simulation scripts provided with the core. Table 15-8: Functional Directory (Contd) Table 15-9: Timing Directory <component_name>/drivers/v2_04_a drivers/avb_v2_04_a/data drivers/avb_v2_04_a/examples drivers/avb_v2_04_a/src Table 15-12: Driver Source Directory Implementation Scripts Simulation Scripts Functional Simulation Timing Simulation Example Design Top-Level Example Design HDL Ethernet Frame Stimulus Ethernet Frame Checker Loopback Module PLB Module Demonstration Test Bench Customizing the Test Bench Simulation Run Time Changing Frame Data Viewing the Simulation Wave Form Chapter 16 Detailed Example Design (EDK format) Directory and File Contents <project directory> <project directory>/<component name> <component name>/doc <component name>/MyProcessorIPLib MyProcessorIPLib/pcores/eth_avb_endpoint_v2_04_a pcores/eth_avb_endpoint_v2_04_a/data pcores/eth_avb_endpoint_v2_04_a/hdl/vhdl pcores/eth_avb_endpoint_v2_04_a/netlist MyProcessorIPLib/drivers/avb_v2_04_a Directory and File Contents drivers/avb_v2_04_a/data drivers/avb_v2_04_a/examples Table 16-7: Driver Data Directory Table 16-8: Driver Example Directory Chapter 16: Detailed Example Design (EDK format) drivers/avb_v2_04_a/src Table 16-9: Driver Source Directory Page Page Appendix A RTC Time Stamp Accuracy Time Stamp Accuracy RTC Real Time Instantaneous Error Page RTC Sampling Error Appendix A: RTC Time Stamp Accuracy Figure A-3: Sampling Position Uncertainty Sampling uncertainty Sample Accuracy Resulting from the Combined Errors