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Xilinx UG492 manual RTC Interrupt Clear Register

Models: UG492

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Chapter 10: Configuration and Status

This register and the registers defined in Table 10-11and in Table 10-12are linked. When this nanoseconds value register is read, the entire RTC (including the seconds field) is sampled.

Table 10-10:Current RTC Nanoseconds Value (PLB_base_address + 0x2814)

Bit no	Default	Access	Description

29-0	0	RO	Current Value of the synchronized RTC nanoseconds
			field.
			Note: A read from this register samples the entire RTC
			counter (synchronized) so that the Epoch and Seconds
			field are held static for a subsequent read.

31-30	0	RO	Unused

Table 10-11describes the lower 32-bits of the seconds value register for the seconds field of the “Real Time Clock.” When read, this returns the latest value of the counter.

This register and the registers defined in Table 10-10and in Table 10-12are linked. When the nanoseconds value register is read (see Table 10-10), the entire RTC is sampled.

Table 10-11:Current RTC Seconds Field Value bits [31:0] (PLB_base_address + 0x2818)

Bit no	Default	Access	Description

31-0	0	RO	Sampled Value of the synchronized RTC Seconds field
			(bits 31-0).

Table 10-12describes the upper 16-bits of the seconds value register for the seconds field of the “Real Time Clock.” When read, this returns the latest value of the counter.

This register and the registers defined in Table 10-10and in Table 10-11are linked. When the nanoseconds value register is read (see Table 10-10), the entire RTC is sampled.

Table 10-12:Current RTC Seconds Field Value bits [47:32] (PLB_base_address + 0x281C)

Bit no	Default	Access	Description

15-0	0	RO	Sampled Value of the synchronized RTC Seconds field
			(bits 47-32).

32-16	0	RO	Unused

RTC Interrupt Clear Register

Table 10-13describes the control register defined for the interrupt_ptp_timer signal, the periodic interrupt signal which is raised by the “Real Time Clock.”

Table 10-13:RTC Interrupt Clear Register (PLB_base_address + 0x2820)

Bit no	Default	Access	Description

0	0	WO	Write ANY value to bit 0 of this register to clear the
			interrupt_ptp_timer Interrupt signal. This bit always
			returns 0 on read.

31-1	0	RO	Unused

96	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

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Xilinx UG492 manual RTC Interrupt Clear Register

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23Revision History Date Version RevisionTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home NetworkConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This GuideConventions TypographicalOnline Document ConventionsConvention Meaning or Use Example List of Abbreviations Acronym Spelled OutConventions Acronym Spelled Out VhdlPreface About This Guide Introduction System RequirementsAbout the Core WindowsRecommended Design Experience Additional Core ResourcesTechnical Support FeedbackDocument FeedbackIntroduction Licensing the Core Before you Begin License OptionsSimulation Only Full System Hardware EvaluationInstalling the License File Obtaining Your License KeyOverview of Ethernet Audio Video Bridging 1Example AVB Home NetworkAVB Specifications P802.1ASOverview of Ethernet Audio Video Bridging AVB Specifications P802.1QavTalker Assumptions Listener AssumptionsTypical Implementation P802.1QatTypical Implementation UG492 July 23 Generating the Core Ethernet AVB GUIComponent Name Core Delivery FormatGenerating the Core Number of PLB Masters PLB Base AddressEthernet AVB GUI Parameter Values in the XCO File Output GenerationCore Architecture Standard Core Generator Format Core ArchitectureEDK pcore Format EDK pcore FormatFunctional Block Description PLB InterfaceAV Traffic Interface Legacy Traffic InterfaceTx Arbiter Rx SplitterMAC Header Filters Functional Block DescriptionPrecise Timing Protocol Blocks Tx PTP Packet BuffersTx Time Stamp Rx PTP Packet BuffersRTC Software Drivers Tri-Mode Ethernet MACsClocks and Reset 1Clocks and Resets Signal Direction DescriptionCore Interfaces Core InterfacesLegacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals3Legacy Traffic Signals Receiver Path Direction Description AV Traffic Transmitter Path Signals 3Legacy Traffic Signals Receiver Path4AV Traffic Signals Transmitter Path Direction Description AV Traffic Receiver Path Signals 5AV Traffic Signals Receiver Path Direction DescriptionTri-Mode Ethernet MAC Client Interface MAC Transmitter InterfaceMAC Receiver Interface MAC Management InterfaceProcessor Local Bus PLB Interface PLB Interface PIN Name Direction DescriptionEthernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction DescriptionPTP Signals Signal Direction DescriptionEthernet AVB Endpoint Transmission Tx Legacy Traffic I/FError Free Legacy Frame Transmission Ethernet AVB Endpoint TransmissionErrored Legacy Frame Transmission Tx AV Traffic I/FTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Tx Arbiter OverviewCredit Based Traffic Shaping Algorithm Tx Arbiter4Credit-based Shaper Operation Tx Arbiter Bandwidth Control IdleSlopeSendSlope HiLimit LoLimitEthernet AVB Endpoint Reception Rx SplitterRx Legacy Traffic I/F Error Free Legacy Frame Reception Ethernet AVB Endpoint ReceptionErrored Legacy Frame Reception Legacy MAC Header FiltersOverview of Operation Rx Legacy Traffic I/F3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA MatchPartial Destination Address DA Match 5Filtering of Frames with a Partial DA MatchVlan Priority Match Any Other CombinationsError Free AV Traffic Reception Rx AV Traffic I/FRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic InterfaceReal Time Clock and Time Stamping Real Time ClockReal Time Clock and Time Stamping RTC Implementation Increment of Nanoseconds FieldReal Time Clock Increment of the Seconds Field Controlled Frequency RTCSynchronized RTC Time Stamping Logic Time Stamping LogicTime Stamp Sampling Position of MAC Frames 3Time Stamping PositionIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet BufferPrecise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer StructureRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Configuration and Status Processor Local Bus InterfaceSingle Read Transaction Configuration and Status 1Single Read TransactionSingle Write Transaction Processor Local Bus InterfacePLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address SpaceEthernet Audio Video End Point Configuration Registers Ethernet AVB Endpoint Address SpaceRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address SpaceRx PTP Packet Control Register Rx Filtering Control RegisterTx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control RegisterRTC Offset Control Registers RTC Increment Value Control Register Current RTC Value RegistersRTC Interrupt Clear Register Software Reset Register Phase Adjustment RegisterPTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access DescriptionMAC Configuration and Statistics Tri-Mode Ethernet MAC Address SpaceMAC Address Filter Registers MAC Mdio Registers 102 Constraining the Core Required ConstraintsPeriod Constraints for Clock Nets PLBclkHostclk TxclkTimespecs for Critical Logic within the Core RtcclkRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System IntegrationLogiCORE IP Tri-Mode Ethernet MAC Soft Core Tri-Mode Ethernet MAC Core GenerationSystem Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics114 Connections Including Ethernet Statistics GNDLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLBUsing an ISE Software Top-Level Project PLBEthernet AVB Endpoint User Guide 123 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Xpslltemac configurationIntroduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemacEthernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MACEND Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock MasterClock Slave Software System IntegrationDriver Instantiation Software DriversInterrupt Service Routine Connections Software System IntegrationEthernet AVB Endpoint Setup When Using a LogiCORE IP Tri-Mode Ethernet MACCore Initialization System-Specific Defines in xavbhw.hSetting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback HandlerStarting and Stopping the AVB Drivers Quick Start Example Design OverviewQuick Start Example Design 1Ethernet AVB Endpoint Example Design and Test BenchGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Setting up for Simulation Functional Simulation Implementing the Example DesignSimulating the Example Design Implementing the Example DesignWhat’s Next? Timing SimulationDetailed Example Design Standard Format Project directoryDirectory and File Contents Project directory/component name Component name/docComponent name/example design Component name/implement 5Implement Directory Name DescriptionImplement/results Component name/simulationSimulation/functional 6Results Directory Name DescriptionSimulation/timing Name DescriptionComponentname/drivers/v204a Drivers/avbv204a/dataDrivers/avbv204a/examples 11Driver Example Directory Name DescriptionDrivers/avbv204a/src Implementation Scripts Simulation ScriptsImplementation Scripts Example Design Example Design HDL for the Ethernet AVB EndpointTop-Level Example Design HDL Ethernet Frame StimulusExample Design Ethernet Frame Checker Loopback ModulePLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test BenchCustomizing the Test Bench Simulation Run TimeChanging Frame Data 3Simulator Wave Window Contents Viewing the Simulation Wave FormDetailed Example Design EDK format Detailed Example Design EDK format Component name/MyProcessorIPLib MyProcessorIPLib/pcores/ethavbendpointv204aPcores/ethavbendpointv204a/data Pcores/ethavbendpointv204a/hdl/vhdl Pcores/ethavbendpointv204a/netlistMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Real Time Instantaneous Error RTC Time Stamp AccuracyTime Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp AccuracyRTC Sampling Error Time Stamp AccuracyFigure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy172