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Chapter 14: Quick Start Example Design
The Ethernet AVB Endpoint example design has been tested using Xilinx® ISE® software v12.2, Cadence Incisive Enterprise Simulator (IES) v9.2, Mentor Graphics ModelSim v 6.5c, and Synopsys VCS and VCS MX 2009.12.
Demonstration Test Bench
Clock
and
Reset
generation
Statistic
Gathering
Example Design Top Level |
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Tx frame | AV traffic |
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stimulus |
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Tx frame |
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| loopback |
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| module | |
stimulus |
| Ethernet | |
| legacy |
| AVB |
| traffic | Endpoint | |
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| LogiCORE | |
Rx frame | legacy |
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|
traffic |
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| |
checker |
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Rx frame |
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checker | AV traffic |
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| Interrupts | PLB | |
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| PLB |
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| module |
Figure 14-1: Ethernet AVB Endpoint Example Design and Test Bench
138 | www.xilinx.com | Ethernet AVB Endpoint User Guide |
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| UG492 July 23, 2010 |