Xilinx UG492 manual Ethernet AVB Endpoint User Guide 117

Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs

Connections Without Ethernet Statistics

Ethernet AVB Endpoint	Block-level Wrapper
Core Netlist	(from Virtex-5 Embedded Tri-mode
	Ethernet MAC Wrapper)
	CLIENTEMAC0PAUSEREQ
	CLIENTEMAC0PAUSEVAL[15:0]
GND
tx_clk	TX_CLK_0
tx_clk_en	TX_CLIENT_CLK_ENABLE_0
tx_data[7:0]	CLIENTEMAC0TXD[7:0]	EMAC0CLIENTTXSTATS
tx_data_valid	CLIENTEMAC0TXDVLD	EMAC0CLIENTTXSTATSVLD
tx_underrun	CLIENTEMAC0TXUNDERRUN	EMAC0CLIENTTXSTATSBYTEVLD
tx_ack	EMAC0CLIENTTXACK
NC	EMAC0CLIENTTXCOLLISION
NC	EMAC0CLIENTTXRETRANSMIT
	CLIENTEMAC0IFGDELAY
GND
rx_clk	GMII_RX_CLK0
rx_clk_en	RX_CLIENT_CLK_ENABLE_0
rx_data[7:0]	EMAC0CLIENTRXD[7:0]	EMAC0CLIENTRXSTATS[6:0]
rx_data_valid	EMAC0CLIENTRXDVLD	EMAC0CLIENTRXSTATSVLD
rx_frame_good	EMAC0CLIENTRXGOODFRAME	EMAC0CLIENTRXSTATSBYTEVLD
rx_frame_bad	EMAC0CLIENTRXBADFRAME
host_opcode[1:0]	HOSTOPCODE[1:0]
host_addr[9:0]	HOSTADDR[9:0]
host_wr_data[31:0]	HOSTWRDATA[31:0]
host_req	HOSTREQ
host_miim_sel	HOSTMIIMSEL
host_miim_rdy	HOSTMIIMRDY
host_rd_data_mac[31:0]	HOSTRDDATA[31:0]
host_rd_data_stats[31:0]
host_stats_lsw_rdy	HOSTCLK
host_stats_msw_rdy	HOSTEMAC1SEL
host_clk
GND
GND
host_clk

Figure 12-3:Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC

(without Ethernet Statistics)

NC NC NC

NC NC NC

Figure 12-3illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (EMAC) core when not using the Ethernet Statistics core. Figure 12-3provides detail for the connections between the two cores which were shown in Figure 5-1.

All connections, as shown, are logic-less connections. Because the AVB standard does not include support for half-duplex or flow control operation, the relevant half-duplex/flow- control signals of the EMAC can be left unused: inputs can be tied to logic 0, outputs can be left unconnected.

Ethernet AVB Endpoint User Guide www.xilinx.com 117

UG492 July 23, 2010