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Xilinx UG492 manual Introduction

Models: UG492

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Chapter 1: Introduction

26	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

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Xilinx UG492 manual Introduction

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23Revision History Date Version RevisionTable of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home NetworkConstraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This GuideConventions TypographicalConvention Meaning or Use Example Online DocumentConventions List of Abbreviations Acronym Spelled OutConventions Acronym Spelled Out VhdlPreface About This Guide About the Core IntroductionSystem Requirements WindowsTechnical Support Recommended Design ExperienceAdditional Core Resources FeedbackDocument FeedbackIntroduction Simulation Only Licensing the CoreBefore you Begin License Options Full System Hardware EvaluationInstalling the License File Obtaining Your License KeyOverview of Ethernet Audio Video Bridging 1Example AVB Home NetworkOverview of Ethernet Audio Video Bridging AVB SpecificationsP802.1AS Talker Assumptions AVB SpecificationsP802.1Qav Listener AssumptionsTypical Implementation P802.1QatTypical Implementation UG492 July 23 Generating the Core Ethernet AVB GUIGenerating the Core Component NameCore Delivery Format Ethernet AVB GUI Number of PLB MastersPLB Base Address Parameter Values in the XCO File Output GenerationCore Architecture Standard Core Generator Format Core ArchitectureEDK pcore Format EDK pcore FormatAV Traffic Interface Functional Block DescriptionPLB Interface Legacy Traffic InterfaceMAC Header Filters Tx ArbiterRx Splitter Functional Block DescriptionTx Time Stamp Precise Timing Protocol BlocksTx PTP Packet Buffers Rx PTP Packet BuffersRTC Software Drivers Tri-Mode Ethernet MACsCore Interfaces Clocks and Reset1Clocks and Resets Signal Direction Description Core Interfaces3Legacy Traffic Signals Receiver Path Direction Description Legacy Traffic Transmitter Path SignalsLegacy Traffic Receiver Path Signals 4AV Traffic Signals Transmitter Path Direction Description AV Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path Tri-Mode Ethernet MAC Client Interface AV Traffic Receiver Path Signals5AV Traffic Signals Receiver Path Direction Description MAC Transmitter InterfaceMAC Receiver Interface MAC Management InterfaceProcessor Local Bus PLB Interface PLB Interface PIN Name Direction DescriptionEthernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction DescriptionPTP Signals Signal Direction DescriptionEthernet AVB Endpoint Transmission Tx Legacy Traffic I/FError Free Legacy Frame Transmission Ethernet AVB Endpoint TransmissionTx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Credit Based Traffic Shaping Algorithm Tx ArbiterOverview Tx Arbiter4Credit-based Shaper Operation SendSlope Tx Arbiter Bandwidth ControlIdleSlope HiLimit LoLimitRx Legacy Traffic I/F Ethernet AVB Endpoint ReceptionRx Splitter Error Free Legacy Frame Reception Ethernet AVB Endpoint ReceptionOverview of Operation Errored Legacy Frame ReceptionLegacy MAC Header Filters Rx Legacy Traffic I/F3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA MatchPartial Destination Address DA Match 5Filtering of Frames with a Partial DA MatchVlan Priority Match Any Other CombinationsRx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic InterfaceReal Time Clock and Time Stamping Real Time ClockReal Time Clock and Time Stamping Real Time Clock RTC ImplementationIncrement of Nanoseconds Field Synchronized RTC Increment of the Seconds FieldControlled Frequency RTC Time Stamping Logic Time Stamping LogicTime Stamp Sampling Position of MAC Frames 3Time Stamping PositionIEEE1722 Real Time Clock Format IEEE1722 Real Time Clock FormatReal Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet BufferPrecise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer StructureRx PTP Packet Buffer Rx PTP Packet Buffer2Rx PTP Packet Buffer Single Read Transaction Configuration and StatusProcessor Local Bus Interface Configuration and Status 1Single Read TransactionSingle Write Transaction Processor Local Bus InterfacePLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address SpaceRx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration RegistersEthernet AVB Endpoint Address Space Tx PTP Packet Buffer Address SpaceRx PTP Packet Control Register Rx Filtering Control RegisterRTC Offset Control Registers Tx Arbiter Send Slope Control RegisterTx Arbiter Idle Slope Control Register RTC Increment Value Control Register Current RTC Value RegistersRTC Interrupt Clear Register Software Reset Register Phase Adjustment RegisterPTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access DescriptionMAC Address Filter Registers MAC Configuration and StatisticsTri-Mode Ethernet MAC Address Space MAC Mdio Registers 102 Constraining the Core Required ConstraintsHostclk Period Constraints for Clock NetsPLBclk TxclkRequired Constraints Timespecs for Critical Logic within the CoreRtcclk Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System IntegrationSystem Integration LogiCORE IP Tri-Mode Ethernet MAC Soft CoreTri-Mode Ethernet MAC Core Generation Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics114 Connections Including Ethernet Statistics GNDLogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLBUsing an ISE Software Top-Level Project PLBEthernet AVB Endpoint User Guide 123 Introduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACXpslltemac configuration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemacEthernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MACEND Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock MasterDriver Instantiation Clock SlaveSoftware System Integration Software DriversInterrupt Service Routine Connections Software System IntegrationCore Initialization Ethernet AVB Endpoint SetupWhen Using a LogiCORE IP Tri-Mode Ethernet MAC System-Specific Defines in xavbhw.hSetting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback HandlerStarting and Stopping the AVB Drivers Quick Start Example Design OverviewQuick Start Example Design 1Ethernet AVB Endpoint Example Design and Test BenchGenerating the Core 2Ethernet AVB Endpoint Core Customization Screen Simulating the Example Design Setting up for Simulation Functional SimulationImplementing the Example Design Implementing the Example DesignWhat’s Next? Timing SimulationDetailed Example Design Standard Format Project directoryDirectory and File Contents Component name/example design Project directory/component nameComponent name/doc Component name/implement 5Implement Directory Name DescriptionSimulation/functional Implement/resultsComponent name/simulation 6Results Directory Name DescriptionSimulation/timing Name DescriptionDrivers/avbv204a/examples Componentname/drivers/v204aDrivers/avbv204a/data 11Driver Example Directory Name DescriptionDrivers/avbv204a/src Implementation Scripts Implementation ScriptsSimulation Scripts Example Design Example Design HDL for the Ethernet AVB EndpointExample Design Top-Level Example Design HDLEthernet Frame Stimulus Ethernet Frame Checker Loopback ModulePLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test BenchChanging Frame Data Customizing the Test BenchSimulation Run Time 3Simulator Wave Window Contents Viewing the Simulation Wave FormDetailed Example Design EDK format Detailed Example Design EDK format Pcores/ethavbendpointv204a/data Component name/MyProcessorIPLibMyProcessorIPLib/pcores/ethavbendpointv204a MyProcessorIPLib/drivers/avbv204a Pcores/ethavbendpointv204a/hdl/vhdlPcores/ethavbendpointv204a/netlist 5Driver Data Directory Name Description8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 Time Stamp Accuracy RTC Real Time Instantaneous ErrorRTC Time Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp AccuracyRTC Sampling Error Time Stamp AccuracyFigure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy172