Chapter 15: Detailed Example Design (Standard Format)

The data field of the frame is designed to create a simple 8-bit binary counter that continues seamlessly across consecutive Ethernet frames. The Ethernet Frame Stimulus block is designed to produce frames at full line rate to fully stress the core.

Ethernet Frame Checker

The following files describe the Ethernet Frame Checker logic.

VHDL

<project_dir>/<component_name>/example_design/rx_frame_checker.vhd

Verilog

<project_dir>/<component_name>/example_design/rx_frame_checker.v

This module contains the logic to check a received Ethernet frame against expected parameters. The MAC header fields of this expected frame are defined by generics (Destination Address, Source Address, Length/Type); the VLAN field is optional.

Additionally, the expected length of the Ethernet frame can also be set using a parameter.

The data field of the frame is expected to consist of a simple 8-bit binary counter which continues seamlessly across consecutive Ethernet frames.

This logic is designed to check against the frames generated by the tx_frame_stimulus module; identical parameters must be passed into both modules to obtain a match.

Loopback Module

The following files describe the Loopback module.

VHDL

<project_dir>/<component_name>/example_design/temac_loopback_shim.vhd

Verilog

<project_dir>/<component_name>/example_design/temac_loopback_shim.v

This logic implements a simple logic shim to provide a frame loopback function at the MAC client Interface. This logic does NOT implement a MAC and should be replaced with a real MAC in any real implementations.

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Ethernet AVB Endpoint User Guide

 

 

UG492 July 23, 2010

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Xilinx UG492 manual Ethernet Frame Checker, Loopback Module