Xilinx UG492 manual 118

Chapter 12: System Integration

Because the EMAC core can often be used in different clocking modes, note the following:

•The Ethernet transmitter client clock domain must always be connected to the

tx_clk input of the Ethernet AVB Endpoint core. Additionally, the transmitter clock enable, as used with the EMAC, must always be connected to the tx_clk_en input of the Ethernet AVB Endpoint core.

•The Ethernet receiver client clock domain must always be connected to the rx_clk input of the Ethernet AVB Endpoint core. Additionally, the receiver clock enable, as used with the EMAC, must always be connected to the rx_clk_en input of the Ethernet AVB Endpoint core.

•The host_clk input of the Ethernet AVB Endpoint and the HOSTCLK input the EMAC must always share the same clock source.

Connections Including Ethernet Statistics

Ethernet AVB Endpoint				Block-level Wrapper
	Core Netlist			(from Virtex-5 Embedded Tri-mode
				Ethernet MAC Wrapper)
				CLIENTEMAC0PAUSEREQ
				CLIENTEMAC0PAUSEVAL[15:0]
			GND
		tx_clk		TX_CLK_0
	tx_clk_en			TX_CLIENT_CLK_ENABLE_0	EMAC0CLIENTTXSTATS
	tx_data[7:0]			CLIENTEMAC0TXD[7:0]	EMAC0CLIENTTXSTATSVLD
	tx_data_valid			CLIENTEMAC0TXDVLD	EMAC0CLIENTTXSTATSBYTEVLD
	tx_underrun			CLIENTEMAC0TXUNDERRUN
		tx_ack		EMAC0CLIENTTXACK
			NC	EMAC0CLIENTTXCOLLISION
			NC	EMAC0CLIENTTXRETRANSMIT
				CLIENTEMAC0IFGDELAY
		rx_clk	GND
				GMII_RX_CLK0
	rx_clk_en			RX_CLIENT_CLK_ENABLE_0	EMAC0CLIENTRXSTATS[6:0]
	rx_data[7:0]			EMAC0CLIENTRXD[7:0]	EMAC0CLIENTRXSTATSVLD
	rx_data_valid			EMAC0CLIENTRXDVLD	EMAC0CLIENTRXSTATSBYTEVLD
	rx_frame_good			EMAC0CLIENTRXGOODFRAME
	rx_frame_bad			EMAC0CLIENTRXBADFRAME
	host_opcode[1:0]			HOSTOPCODE[1:0]
	host_addr[9:0]			HOSTADDR[9:0]
	host_wr_data[31:0]			HOSTWRDATA[31:0]
		host_req		HOSTREQ
	host_miim_sel			HOSTMIIMSEL
	host_miim_rdy			HOSTMIIMRDY
	host_rd_data_mac[31:0]			HOSTRDDATA[31:0]
	hos_rd_data_stats[31:0]			HOSTCLK
	host_stats_lsw_rdy
	host_stats_msw_rdy			HOSTEMAC1SEL
		host_clk
	GND
				Ethernet Statistics Block-level Wrapper
	host_clk			(from Ethernet Statistics Example Design)
				host_opcode[1:0]	txclientclkin
				host_addr[9:0]	clienttxstats
					clienttxstatsvld
				host_req	clienttxstatsbytevalid
				host_miim_sel	rxclientclkin
				host_miim_rdy
				host_rd_data[31:0]	clientrxstats[6:0]
				host_stats_lsw_rdy	clientrxstatsvld
				host_stats_msw_rdy	clientrxstatsbytevalid
				host_clk	clientrxdvld

Figure 12-4:Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC and Ethernet Statistic

Core

118	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010