Xilinx UG492 manual

Chapter 6: Ethernet AVB Endpoint Transmission

tx_clk

tx_clk_enable

av_tx_data[7:0]

av_tx_data_valid

av_tx_done

av_tx_ack

DA

SA

L/T

DATA

DA

Figure 6-3:Normal Frame Transmission across the AV Traffic Interface

Figure 6-3illustrates the timing of a normal frame transfer. When the AV client initiates a frame transmission, it places the first column of data onto the av_tx_data[7:0] port and asserts a logic 1 onto av_tx_valid.

After the Ethernet AVB Endpoint core reads the first byte of data, it asserts the av_tx_ack signal. On the next and subsequent rising clock edges, the client must provide the remainder of the data for the frame. The end of frame is signalled to the core by taking the av_tx_valid to logic 0.

In Figure 6-3, following the end of frame transmission, the av_tx_done signal is held low, which indicates to the “Tx Arbiter” that another AV frame is queued. Unless the configurable bandwidth restrictions have been exceeded, this parks the “Tx Arbiter” onto the AV traffic queue. Figure 6-3then illustrates the client asserting the av_tx_valid signal to request a subsequent frame, and the frame transmission cycle of Figure 6-3repeats. However, if no further AV traffic frames are queued, the av_tx_done signal should be set to logic 1 immediately following the end of frame transmission. This than allows the “Tx Arbiter” to schedule legacy traffic transmission (if any legacy frames are queued).

If, following the end of frame reception, the bandwidth allocation for AV traffic has been exceeded, the “Tx Arbiter” switches to service the legacy traffic regardless of the state of the av_tx_done signal.

For this reason, the av_tx_done signal should be considered an aid to the “Tx Arbiter” to help make best use of the available network bandwidth. Asserting this signal after all AV traffic has been serviced immediately allows the “Tx Arbiter” to service the legacy traffic. This helps achieve in excess of the 25% minimum allocation for the legacy traffic. However, holding off the assertion of av_tx_done will not act as cheat mode to exceed the maximum bandwidth allocation for the AV traffic.

60	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

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Xilinx UG492 manual 3Normal Frame Transmission across the AV Traffic Interface

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23 Revision History Date Version Revision Table of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home Network Constraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This Guide Conventions Typographical Online Document ConventionsConvention Meaning or Use Example List of Abbreviations Acronym Spelled Out Conventions Acronym Spelled Out Vhdl Preface About This Guide Introduction System RequirementsAbout the Core Windows Recommended Design Experience Additional Core ResourcesTechnical Support Feedback Document Feedback Introduction Licensing the Core Before you Begin License OptionsSimulation Only Full System Hardware Evaluation Installing the License File Obtaining Your License Key Overview of Ethernet Audio Video Bridging 1Example AVB Home Network AVB Specifications P802.1ASOverview of Ethernet Audio Video Bridging AVB Specifications P802.1QavTalker Assumptions Listener Assumptions Typical Implementation P802.1Qat Typical Implementation UG492 July 23 Generating the Core Ethernet AVB GUI Component Name Core Delivery FormatGenerating the Core Number of PLB Masters PLB Base AddressEthernet AVB GUI Parameter Values in the XCO File Output Generation Core Architecture Standard Core Generator Format Core Architecture EDK pcore Format EDK pcore Format Functional Block Description PLB InterfaceAV Traffic Interface Legacy Traffic Interface Tx Arbiter Rx SplitterMAC Header Filters Functional Block Description Precise Timing Protocol Blocks Tx PTP Packet BuffersTx Time Stamp Rx PTP Packet Buffers RTC Software Drivers Tri-Mode Ethernet MACs Clocks and Reset 1Clocks and Resets Signal Direction DescriptionCore Interfaces Core Interfaces Legacy Traffic Transmitter Path Signals Legacy Traffic Receiver Path Signals3Legacy Traffic Signals Receiver Path Direction Description AV Traffic Transmitter Path Signals 3Legacy Traffic Signals Receiver Path4AV Traffic Signals Transmitter Path Direction Description AV Traffic Receiver Path Signals 5AV Traffic Signals Receiver Path Direction DescriptionTri-Mode Ethernet MAC Client Interface MAC Transmitter Interface MAC Receiver Interface MAC Management Interface Processor Local Bus PLB Interface PLB Interface PIN Name Direction Description Ethernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction Description PTP Signals Signal Direction Description Ethernet AVB Endpoint Transmission Tx Legacy Traffic I/F Error Free Legacy Frame Transmission Ethernet AVB Endpoint Transmission Errored Legacy Frame Transmission Tx AV Traffic I/FTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Tx Arbiter OverviewCredit Based Traffic Shaping Algorithm Tx Arbiter 4Credit-based Shaper Operation Tx Arbiter Bandwidth Control IdleSlopeSendSlope HiLimit LoLimit Ethernet AVB Endpoint Reception Rx SplitterRx Legacy Traffic I/F Error Free Legacy Frame Reception Ethernet AVB Endpoint Reception Errored Legacy Frame Reception Legacy MAC Header FiltersOverview of Operation Rx Legacy Traffic I/F 3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA Match Partial Destination Address DA Match 5Filtering of Frames with a Partial DA Match Vlan Priority Match Any Other Combinations Error Free AV Traffic Reception Rx AV Traffic I/FRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic Interface Real Time Clock and Time Stamping Real Time Clock Real Time Clock and Time Stamping RTC Implementation Increment of Nanoseconds FieldReal Time Clock Increment of the Seconds Field Controlled Frequency RTCSynchronized RTC Time Stamping Logic Time Stamping Logic Time Stamp Sampling Position of MAC Frames 3Time Stamping Position IEEE1722 Real Time Clock Format IEEE1722 Real Time Clock Format Real Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer Structure Rx PTP Packet Buffer Rx PTP Packet Buffer 2Rx PTP Packet Buffer Configuration and Status Processor Local Bus InterfaceSingle Read Transaction Configuration and Status 1Single Read Transaction Single Write Transaction Processor Local Bus Interface PLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space Ethernet Audio Video End Point Configuration Registers Ethernet AVB Endpoint Address SpaceRx PTP Packet Buffer Address Space Tx PTP Packet Buffer Address Space Rx PTP Packet Control Register Rx Filtering Control Register Tx Arbiter Send Slope Control Register Tx Arbiter Idle Slope Control RegisterRTC Offset Control Registers RTC Increment Value Control Register Current RTC Value Registers RTC Interrupt Clear Register Software Reset Register Phase Adjustment Register PTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access Description MAC Configuration and Statistics Tri-Mode Ethernet MAC Address SpaceMAC Address Filter Registers MAC Mdio Registers 102 Constraining the Core Required Constraints Period Constraints for Clock Nets PLBclkHostclk Txclk Timespecs for Critical Logic within the Core RtcclkRequired Constraints Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System Integration LogiCORE IP Tri-Mode Ethernet MAC Soft Core Tri-Mode Ethernet MAC Core GenerationSystem Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics 114 Connections Including Ethernet Statistics GND LogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLB Using an ISE Software Top-Level Project PLB Ethernet AVB Endpoint User Guide 123 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC Xpslltemac configurationIntroduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemac Ethernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC END Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock Master Clock Slave Software System IntegrationDriver Instantiation Software Drivers Interrupt Service Routine Connections Software System Integration Ethernet AVB Endpoint Setup When Using a LogiCORE IP Tri-Mode Ethernet MACCore Initialization System-Specific Defines in xavbhw.h Setting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback Handler Starting and Stopping the AVB Drivers Quick Start Example Design Overview Quick Start Example Design 1Ethernet AVB Endpoint Example Design and Test Bench Generating the Core 2Ethernet AVB Endpoint Core Customization Screen Setting up for Simulation Functional Simulation Implementing the Example DesignSimulating the Example Design Implementing the Example Design What’s Next? Timing Simulation Detailed Example Design Standard Format Project directory Directory and File Contents Project directory/component name Component name/docComponent name/example design Component name/implement 5Implement Directory Name Description Implement/results Component name/simulationSimulation/functional 6Results Directory Name Description Simulation/timing Name Description Componentname/drivers/v204a Drivers/avbv204a/dataDrivers/avbv204a/examples 11Driver Example Directory Name Description Drivers/avbv204a/src Implementation Scripts Simulation ScriptsImplementation Scripts Example Design Example Design HDL for the Ethernet AVB Endpoint Top-Level Example Design HDL Ethernet Frame StimulusExample Design Ethernet Frame Checker Loopback Module PLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test Bench Customizing the Test Bench Simulation Run TimeChanging Frame Data 3Simulator Wave Window Contents Viewing the Simulation Wave Form Detailed Example Design EDK format Detailed Example Design EDK format Component name/MyProcessorIPLib MyProcessorIPLib/pcores/ethavbendpointv204aPcores/ethavbendpointv204a/data Pcores/ethavbendpointv204a/hdl/vhdl Pcores/ethavbendpointv204a/netlistMyProcessorIPLib/drivers/avbv204a 5Driver Data Directory Name Description 8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 RTC Real Time Instantaneous Error RTC Time Stamp AccuracyTime Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp Accuracy RTC Sampling Error Time Stamp Accuracy Figure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy 172