2Rx PTP Packet Buffer | Xilinx UG492 instruction

Chapter 9: Precise Timing Protocol Packet Buffers

The “Software Drivers” provided with the core, using the PLB and dedicated interrupt, will use this interface to decode, and then act on, the received PTP packet information.

Rx PTP Packet Buffers

Buffer Number 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Buffer Base Address
0x0F00
	Single Rx PTP Packet Buffer
0x0E00		Address (+ Buffer Base Address)
	timestamp[31:24]	0xFF
0x0D00	timestamp[23:16]	0xFE
	timestamp[23:16]	0xFE
0x0C00	timestamp[15:8]	0xFD
0x0B00	timestamp[7:0]	0xFC
0x0B00
0x0A00	unused
		frame size
0x0900
0x0800
0x0700
0x0600	PTP Frame Data
	PTP Frame Data
0x0500
0x0400
0x0400
0x0300
0x0200		0x00
0x0200
0x0100
	byte-wide data
0x0000

Figure 9-2:Rx PTP Packet Buffer

86	www.xilinx.com	Ethernet AVB Endpoint User Guide
		UG492 July 23, 2010

Image 86

Xilinx UG492 manual 2Rx PTP Packet Buffer

Contents

LogiCORETM IP Ethernet AVB Endpoint UG492 July 23 Revision History Date Version Revision Table of Contents Generating the Core Precise Timing Protocol Packet Buffers Quick Start Example Design Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Schedule of Figures 1Example AVB Home Network Constraining the Core System Integration Figure A-1RTC Periodic Error Ethernet AVB Endpoint User Guide Schedule of Tables 17Tri-Mode Ethernet MAC and Ethernet Statistics Detailed Example Design EDK format Ethernet AVB Endpoint User Guide Guide Contents About This Guide Conventions Typographical Convention Meaning or Use Example Online DocumentConventions List of Abbreviations Acronym Spelled Out Conventions Acronym Spelled Out Vhdl Preface About This Guide About the Core IntroductionSystem Requirements Windows Technical Support Recommended Design ExperienceAdditional Core Resources Feedback Document Feedback Introduction Simulation Only Licensing the CoreBefore you Begin License Options Full System Hardware Evaluation Installing the License File Obtaining Your License Key Overview of Ethernet Audio Video Bridging 1Example AVB Home Network Overview of Ethernet Audio Video Bridging AVB SpecificationsP802.1AS Talker Assumptions AVB SpecificationsP802.1Qav Listener Assumptions Typical Implementation P802.1Qat Typical Implementation UG492 July 23 Generating the Core Ethernet AVB GUI Generating the Core Component NameCore Delivery Format Ethernet AVB GUI Number of PLB MastersPLB Base Address Parameter Values in the XCO File Output Generation Core Architecture Standard Core Generator Format Core Architecture EDK pcore Format EDK pcore Format AV Traffic Interface Functional Block DescriptionPLB Interface Legacy Traffic Interface MAC Header Filters Tx ArbiterRx Splitter Functional Block Description Tx Time Stamp Precise Timing Protocol BlocksTx PTP Packet Buffers Rx PTP Packet Buffers RTC Software Drivers Tri-Mode Ethernet MACs Core Interfaces Clocks and Reset1Clocks and Resets Signal Direction Description Core Interfaces 3Legacy Traffic Signals Receiver Path Direction Description Legacy Traffic Transmitter Path SignalsLegacy Traffic Receiver Path Signals 4AV Traffic Signals Transmitter Path Direction Description AV Traffic Transmitter Path Signals3Legacy Traffic Signals Receiver Path Tri-Mode Ethernet MAC Client Interface AV Traffic Receiver Path Signals5AV Traffic Signals Receiver Path Direction Description MAC Transmitter Interface MAC Receiver Interface MAC Management Interface Processor Local Bus PLB Interface PLB Interface PIN Name Direction Description Ethernet AVB Endpoint User Guide Interrupt Signals 10Interrupt Signals Direction Description PTP Signals Signal Direction Description Ethernet AVB Endpoint Transmission Tx Legacy Traffic I/F Error Free Legacy Frame Transmission Ethernet AVB Endpoint Transmission Tx AV Traffic I/F Errored Legacy Frame TransmissionTx AV Traffic I/F 3Normal Frame Transmission across the AV Traffic Interface Credit Based Traffic Shaping Algorithm Tx ArbiterOverview Tx Arbiter 4Credit-based Shaper Operation SendSlope Tx Arbiter Bandwidth ControlIdleSlope HiLimit LoLimit Rx Legacy Traffic I/F Ethernet AVB Endpoint ReceptionRx Splitter Error Free Legacy Frame Reception Ethernet AVB Endpoint Reception Overview of Operation Errored Legacy Frame ReceptionLegacy MAC Header Filters Rx Legacy Traffic I/F 3Normal Frame Reception Address Filter Match MAC Header Filter Configuration Single MAC Header Filter Usage Examples Full Destination Address DA Match Partial Destination Address DA Match 5Filtering of Frames with a Partial DA Match Vlan Priority Match Any Other Combinations Rx AV Traffic I/F Error Free AV Traffic ReceptionRx AV Traffic I/F Errored AV Traffic Reception 8Errored Frame Reception across the AV Traffic Interface Real Time Clock and Time Stamping Real Time Clock Real Time Clock and Time Stamping Real Time Clock RTC ImplementationIncrement of Nanoseconds Field Synchronized RTC Increment of the Seconds FieldControlled Frequency RTC Time Stamping Logic Time Stamping Logic Time Stamp Sampling Position of MAC Frames 3Time Stamping Position IEEE1722 Real Time Clock Format IEEE1722 Real Time Clock Format Real Time Clock and Time Stamping Precise Timing Protocol Packet Buffers Tx PTP Packet Buffer Precise Timing Protocol Packet Buffers 1Tx PTP Packet Buffer Structure Rx PTP Packet Buffer Rx PTP Packet Buffer 2Rx PTP Packet Buffer Single Read Transaction Configuration and StatusProcessor Local Bus Interface Configuration and Status 1Single Read Transaction Single Write Transaction Processor Local Bus Interface PLB Address Map and Register Definitions PLB Address Map and Register Definitions Ethernet AVB Endpoint Address Space Rx PTP Packet Buffer Address Space Ethernet Audio Video End Point Configuration RegistersEthernet AVB Endpoint Address Space Tx PTP Packet Buffer Address Space Rx PTP Packet Control Register Rx Filtering Control Register RTC Offset Control Registers Tx Arbiter Send Slope Control RegisterTx Arbiter Idle Slope Control Register RTC Increment Value Control Register Current RTC Value Registers RTC Interrupt Clear Register Software Reset Register Phase Adjustment Register PTP Receiver logic reset. When written with a 16MAC Header Filter Configuration Registers Cont’d Address Default Access Description MAC Address Filter Registers MAC Configuration and StatisticsTri-Mode Ethernet MAC Address Space MAC Mdio Registers 102 Constraining the Core Required Constraints Hostclk Period Constraints for Clock NetsPLBclk Txclk Required Constraints Timespecs for Critical Logic within the CoreRtcclk Inst Ethernet AVB Endpoint User Guide 107 108 Ethernet AVB Endpoint User Guide 109 110 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs System Integration System Integration LogiCORE IP Tri-Mode Ethernet MAC Soft CoreTri-Mode Ethernet MAC Core Generation Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Connections Without Ethernet Statistics 114 Connections Including Ethernet Statistics GND LogiCORE IP Embedded Tri-Mode Ethernet MACs Ethernet AVB Endpoint User Guide 117 118 Virtex-6 Fpga Embedded Tri-Mode Ethernet MAC 120 Using an EDK Project Top Level PLB Using an ISE Software Top-Level Project PLB Ethernet AVB Endpoint User Guide 123 Introduction Using the Xilinx XPS LocalLink Tri-Mode Ethernet MACXpslltemac configuration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview AVB capable xpslltemac Ethernet AVB Endpoint Connections MHS File Syntax 9Connection to the XPS LocalLink Tri-Mode Ethernet MAC END Ethernet AVB Endpoint User Guide 129 130 Software Drivers Clock Master Driver Instantiation Clock SlaveSoftware System Integration Software Drivers Interrupt Service Routine Connections Software System Integration Core Initialization Ethernet AVB Endpoint SetupWhen Using a LogiCORE IP Tri-Mode Ethernet MAC System-Specific Defines in xavbhw.h Setting up SourcePortIdentity and Default TX PTP Messages Setting up GrandMaster Discontinuity Callback Handler Starting and Stopping the AVB Drivers Quick Start Example Design Overview Quick Start Example Design 1Ethernet AVB Endpoint Example Design and Test Bench Generating the Core 2Ethernet AVB Endpoint Core Customization Screen Simulating the Example Design Setting up for Simulation Functional SimulationImplementing the Example Design Implementing the Example Design What’s Next? Timing Simulation Detailed Example Design Standard Format Project directory Directory and File Contents Component name/example design Project directory/component nameComponent name/doc Component name/implement 5Implement Directory Name Description Simulation/functional Implement/resultsComponent name/simulation 6Results Directory Name Description Simulation/timing Name Description Drivers/avbv204a/examples Componentname/drivers/v204aDrivers/avbv204a/data 11Driver Example Directory Name Description Drivers/avbv204a/src Implementation Scripts Implementation ScriptsSimulation Scripts Example Design Example Design HDL for the Ethernet AVB Endpoint Example Design Top-Level Example Design HDLEthernet Frame Stimulus Ethernet Frame Checker Loopback Module PLB Module Demonstration Test Bench 2Ethernet AVB Endpoint Demonstration Test Bench Changing Frame Data Customizing the Test BenchSimulation Run Time 3Simulator Wave Window Contents Viewing the Simulation Wave Form Detailed Example Design EDK format Detailed Example Design EDK format Pcores/ethavbendpointv204a/data Component name/MyProcessorIPLibMyProcessorIPLib/pcores/ethavbendpointv204a MyProcessorIPLib/drivers/avbv204a Pcores/ethavbendpointv204a/hdl/vhdlPcores/ethavbendpointv204a/netlist 5Driver Data Directory Name Description 8Driver Example Directory Name Description 164 Ethernet AVB Endpoint User Guide 165 166 Time Stamp Accuracy RTC Real Time Instantaneous ErrorRTC Time Stamp Accuracy Figure A-1RTC Periodic Error Appendix a RTC Time Stamp Accuracy RTC Sampling Error Time Stamp Accuracy Figure A-3Sampling Position Uncertainty Accuracy Resulting from the Combined Errors Figure A-4Overall Time Stamp Accuracy 172