Core Interfaces

Interrupt Signals

Table 5-10defines the interrupt signals asserted by the core. All interrupts are active high and are automatically asserted. All interrupts, required by the “Software Drivers” delivered with the core, are cleared by software access to an associated configuration register. It is recommended that these interrupts are routed to the input of an EDK Interrupt Controller module as part of the embedded processor subsystem.

Table 5-10:Interrupt Signals

Signal

Direction

Description

 

 

 

interrupt_ptp_timer

Output

This interrupt is asserted every 1/128

 

 

second as measured by the “RTC.” This acts

 

 

as a timer for the PTP software algorithms.

 

 

 

interrupt_ptp_tx

Output

This is asserted following the transmission

 

 

of any PTP packet from the “Tx PTP Packet

 

 

Buffers.”

 

 

 

interrupt_ptp_rx

Output

This is asserted following the reception of

 

 

any PTP packet into the “Rx PTP Packet

 

 

Buffers.”

 

 

 

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Xilinx UG492 manual 10Interrupt Signals Direction Description