Intel 21555 manuals

198 pages1.82 Mb

2221555 Non-Transparent PCI-to-PCI Bridge User Manual
3Contents
- 6Figures
- Tables
11Preface 1
- A brief description of the contents of this manual follows.
- 121.1 Cautions and Notes
- 1.2 Data Units
- 1.3 Numbering
- 131.4 Signal Nomenclature
- 141.5 Register Abbreviations
15Introduction 2
- 2.1 Comparing a 21555 to a Transparent PPB
  - 16
- 182.2 Architectural Overview
  - 2.2.1 Data Buffers
  - 2.2.2 Registers
  - 2.2.3 Control Logic
    - 19Introduction Figure 2 shows the 21555 microarchitecture. Figure 2. 21555 Microarchitecture
- 202.3 Special Applications
  - 2.3.1 Primary Bus VGA Support
  - 2.3.2 Secondary Bus VGA Support
- 2.4 Programming Notes
  - 2.4.1 Addressing
  - 212.4.2 Transaction Forwarding
  - 2.4.3 ROM Access
23Signal Descriptions 3
- 243.1 Primary PCI Bus Interface Signals
  - Table 6. Primary PCI Bus Interface Signals (Sheet 1 of 2)
  - 25Table 6. Primary PCI Bus Interface Signals (Sheet 2 of 2)
- 263.2 Primary PCI Bus Interface 64-Bit Extension Signals
  - 27Table 7. Primary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2)
- 283.3 Secondary PCI Bus Interface Signals
  - 29Table 8. Secondary PCI Bus Interface Signals (Sheet 2 of 2)
- 303.4 Secondary PCI Bus Interface 64-Bit Extension Signals
- 313.5 Miscellaneous Signals
  - Table 10. Miscellaneous Signals
  - Table 9. Secondary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2)
33Address Decoding 4
- 344.1 CSR Address Decoding
- 4.2 Expansion ROM Address Mapping (Decoding)
- 4.3 Memory 0 Transaction Address Decoding
- 424.4 I/O Transaction Address Decoding
  - 4.4.1 Indirect I/O Transaction Generation
  - 4.4.2 Subtractive Decoding of I/O Transactions
- 444.5 Configuration Accesses
  - 4.5.1 Type 0 Accesses to 21555 Configuration Space
  - 454.5.2 Initiation of Configuration Transactions by 21555
    - - Address Decoding
- 474.6 21555 Bar Summary
  - Table 1 2 shows a summary of the 21555 BARs. Table 12. Bar Summary
49PCI Bus Transactions 5
- 5.1 Transactions Overview
- 505.2 Posted Write Transactions
  - 515.2.1 Memory Write Transactions
  - 5.2.2 Memory Write and Invali da t e Transactions
  - 525.2.3 64-bit Extension Posted Write Transaction
  - 5.2.4 Write Performance Tuning Options
    - 5.2.4.1 Memory Write and Invalidate
    - 5.2.4.2 Fast Back-to-Back
- 545.3 Delayed Write Transactions
- 555.4 Delayed Read Transactions
  - 565.4.1 Nonprefetchable Reads
  - 575.4.2 Prefetchable Reads
  - 5.4.3 Prefetchable Read Transactions Using the 64-bit Extension
  - 5.4.4 Read Performance Features and Tuning Options
    - 5.4.4.1 Read Flow-Through
    - 585.4.4.2 Prefetching
- 595.5 64-Bit and 32-Bit Transactions Initiated by the 21555
- 605.6 Target Terminations
  - 5.6.1 Target Terminations Returned by the 21555
  - 5.6.2 Transaction Termination Errors on the Target Bus
- 615.7 Ordering Rules
  - 62
65Initialization Requirements 6
- 6.1 Power Management, Hot-Swap, and Reset Signals
- 666.2 Reset Behavior
  - 67
  - 6.2.1 Central Function During Reset
- 686.3 21555 Initialization
  - 696.3.1 With SROM, Local, and Host Processors
  - 6.3.2 Without Serial Preload
  - 6.3.3 Without Local Processor
  - 6.3.4 Without Local Processor and Serial Preload
  - 6.3.5 Without Host Processor
- 706.4 Power Management Support
  - 716.4.1 Transitions Between Power Management States
  - 6.4.2 PME# Support
  - 6.4.3 Power Management Data Register
- 726.5 CompactPCI Hot-Swap Functionality
  - 6.5.1 Overview of CompactPCI Controller Hardware Interface
  - 736.5.2 Insertion and Removal Process
    - 751 H/W Connected
    - 5 Extracted
    - 0 H/W Disconnected
    - 4b Insertion
    - 2a INS ENUM#
    - 3 Installed
    - 2b Extraction
    - 4a EXT ENUM#
77Clocking 7
- 7.1 Primary and Secondary PCI Bus Clock Signals
- 787.2 21555 Secondary Clock Outputs
- 797.3 66 MHz Support
81Parallel ROM Interface 8
- 8.1 Interface Signals
  - 82Table 21. PROM I nterface Signals (Sheet 1 of 2)
  - 83Table 21. PROM Inter face Signals (Sheet 2 of 2)
- 848.2 Parallel and Serial ROM Connection
- 8.3 PROM Read by CSR Access
- 868.4 PROM Write by CSR Access
- 878.5 PROM Dword Read
- 888.6 Access Time and Strobe Control
- 898.7 Attaching Additional Devices to the ROM Interface
  - 90Figure 18. Attaching Multiple Devices on the ROM Interface
    - 21555
    - Parallel ROM
    - Serial ROM
91Serial ROM Interface 9
- 9.1 SROM Interface Signals
- 9.2 SROMSROM Preload Operation
- 929.3 SROM Configuration Data Preload Format
- 9.4 SROM Operation by CSR Access
  - 95Serial ROM Interface Figure 22. SROM Erase Timing Diagram
  - Figure 23. SROM Erase All Operation
  - Figure 24. SROM Check Status Timing Diagram
97Arbitration 10
- Table 2 4 describes the secondary PCI bus arbitration signals.
- 10.1 Primary PCI Bus Arbitration Signals
  - Table 2 3 describes the primary PCI bus arbitration signals.
- 10.2 Secondary PCI Bus Arbitration Signals
  - Table 23. Primary PCI B us Arbitration Signals
  - Table 24. Secondary PCI Bus Arbitration Signals
- 9810.3 Primary PCI Bus Arbitration
- 10.4 Secondary PCI Bus Arbitration
  - 10.4.1 Secondary Bus Arbitration Using the Internal Arbiter
  - 10010.4.2 Secondary Bus Arbitration Using an External Arbiter
101Interrupt and Scratchpad Registers 11
- 11.1 Primary and Secondary PCI Bus Interrupt Signals
- 11.2 Interrupt Support
- 10311.3 Doorbell Interrupts
- 11.4 Scratchpad Registers
105Error Handling 12
- 12.1 Error Signals
  - This section describes both the primary and secondary PCI bus error signals.
  - 12.1.1 Primary PCI Bus Error Signals
    - Table 2 7 describes the primary PCI bus error signals. Table 27. Primary PCI Bus Error Signals
  - 10612.1.2 Secondary PCI Bus Error Signals
- 10712.2 Parity Errors
  - 108Table 29. Parity Error Responses (Sheet 2 of 3)
  - 109Table 29. Parity Error Responses (Sheet 3 of 3)
- 11012.3 System Error (SERR#) Reporting
111JTAG Test Port 13
- 13.1 JTAG Signals
- 11213.2 Test Access Port Controller
  - 13.2.1 Initialization
113I2O Support 14
- 14.1 Inbound Message Passing
  - 114
- 11514.2 Outbound Message Passing
- 11614.3 Notes
119VPD Support 15
- 15.1 Reading VPD Information
- 12015.2 Writing VPD Information
121List of Registers 16
- 16.1 Register Summary
- 12216.2 Configuration Registers
- 12616.3 Control and Status Registers
  - Table 33. CSR Address Map (Sheet 1 of 5)
  - Table 32. Configuration Space Address Register (Sheet 5 of 5)
  - 127Table 33. CSR Address Map (Sheet 2 of 5)
  - 128Table 33. CSR Address Map (Sheet 3 of 5)
  - 129Table 33. CSR Address Map (Sheet 4 of 5)
- 13016.4 Address Decoding
  - 16.4.1 Primary and Secondary Address
    - Table 34. Primary CSR and Downstream Memory 0 Bara (Sheet 1 of 2)
    - Table 33. CSR Address Map (Sheet 5 of 5)
    - 131Table 35. Secondary CSR Memory BARsa (Sheet 1 of 2)
    - Table 34. Primary CSR and Downstream Memory 0 Bara (Sheet 2 of 2)
    - 132Table 36. Primary and Secondary CSR I/O Bars
    - Table 35. Secondary C SR Memory BARsa (Sheet 2 of 2)
    - 133Table 37. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR
    - 134Table 38. Downstr eam Memory 2 and 3 BAR, and Upstream Memory 1 BAR
    - 135Table 39. Upper 32 Bits Downstrea m Memory 3 Bar
    - Table 40. Upstream Memory 2 Bar
    - 136Tabl e 4 1. Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register
    - 137Tabl e 4 2. Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register
      - These registers are also mapped in the 21555 I/O and memory CSR space.
    - 138Table 43. Downstr eam I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers
    - 139Table 44. Downstream Me mory 0, 2, 3, and Upstream Memory 1 Setup Registers
  - 14016.4.2 Configuration Transaction Generation Registers
    - 141Table 46. Downstream and Upstream Configuration Address Registers
    - 142Table 47. Downstream Configuration Data and Upstream Configuration Data Registers
    - Table 48. Configuration Own Bits Register
    - 143Table 49. Configuration CSR (Sheet 1 of 2)
    - Table 48. Configuration Own Bits Register
    - 144Table 50. Downstr eam I/O Address and Upstream I/O Address Registers
    - Table 49. Configuration CSR (Sheet 2 of 2)
    - 145Table 51. Downstream I/O Data and Upstream I/O Data Registers
    - Table 52. I/O Own Bits Registers
    - 146Tabl e 53 . I/ O C SR
    - Table 54. Lookup Table Offset Register
- 14716.5 PCI Registers
  - The registers described in this section are shared between the primary and secondary interfaces.
  - 16.5.1 Configuration Registers
    - Table 55. Lookup Table Data Register
    - Table 56. Upstream Memory 2 Lookup Table
    - 148Table 57. Prim ary Interface Configuration Space Address Map
    - Table 58. Seco ndary Interface Configuration Space Address Map
    - Table 59. Vendor ID Register
    - Table 60. Devic e ID Register
  - 14916.5.2 Primary and Secondary Command Registers
    - Table 61. Primary and Secondary Command Registers (Sheet 1 of 2)
    - 150Table 62. Primary and Secondary Status Registers
    - Table 61. Primary and Secondary Command Registers (Sheet 2 of 2)
    - 151Table 63. Revision ID ( Rev ID) Register
    - Table 62. Primary and Secondary Status Registers
    - 152Table 64. Primary and Secondary Class Code Registers
    - Table 65. Primary and Secondary Cache Line Size Registers
    - 153Table 66. Primary Late ncy and Secondary Master Latency Timer Registers
    - Table 67. Header Type Register
    - Table 68. BiST Regist er
    - 154Table 69. Subsystem Vendor ID Register
    - Table 70. Subsys tem ID Register
    - Table 71. Enhanced Capabilities Pointe r Register
    - Table 72. Primary and Secondary Interrupt Line Registers
      - 21555 Non-Transparent PCI-to-PCI Bridge User Manual 155
    - 155Table 73. Primary and Secondary Interrupt Pin Registers
    - Table 74. Primary and Secondary Minimum Grant Registers
    - Table 75. Primary and Secondary Maximum Latency Registers
  - 15616.5.3 Device-Specific Control and Status Registers
    - This section contains information about the device-specific control and status registers.
    - Table 76. Devic e-Specific Control and Status Address Map
    - Table 77. Chip Control 0 Register (Sheet 1 of 4)
    - 157Table 77. Chip Control 0 Register (Sheet 2 of 4)
    - 158Table 77. Chip Control 0 Register (Sheet 3 of 4)
    - 159Table 77. Chip Control 0 Register (Sheet 4 of 4)
    - 160Table 78. Chip Control 1 Register (Sheet 1 of 3)
    - 161Table 78. Chip Control 1 Register (Sheet 2 of 3)
    - 162Table 79. Chip Status Register
    - Table 78. Chip Control 1 Register (Sheet 3 of 3)
    - 163Table 79. Chip Status Register
    - 164Table 80. Generic Own Bits Register
- 16516.6 I2O Registers
  - Table 82. I2O Outbound Post_List Interrupt Mask
  - Table 83. I2O Inbound Post_List Status
  - 166Table 84. I2O Inbound Post_List Interrupt Mask
  - Table 85. I2O Inbound Queue
  - Table 86. I2O Outbound Queue
  - 167Table 87. I2O Inbound Free_List Head Pointer
  - Table 88. I2O Inbound Post_List Tail Pointer
  - Table 89. I2O Outbound Free_List Tail Pointer
  - Table 90. I2O Outbound Post_List Head Pointer
  - 168Table 91. I2O Inbound Post_List Counter
  - Table 92. I2O Inbound Free_List Counter
  - 169Table 93. I2O Outbound Post_List Counter
  - Table 94. I2O Outbound Free_List Counter
- 17016.7 Interrupt Registers
  - Table 96. Chip Set IRQ Mask Register
  - 171Table 97. Chip Clear IRQ Mask Register
  - Table 98. Upstream Page Boundary IRQ 0 Register
  - 172Table 99. Upstream Page Bo undary IRQ 1 Register
  - Table 100. Upstream Page Boundary IRQ Mask 0 Register
  - Table 101. Upstream Page Boundary IRQ Mask 1 Register
  - 173Table 102. Primary Clear IRQ and Secondary Clear IRQ Registers
  - Table 103. Primary Set IRQ and Secondary Set IRQ Registers
- 17416.8 Scratchpad Registers
  - See Chapter 11 for theory of operation information.
  - Table 104. Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers
  - Table 105. Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
  - Table 106. Scratchpad 0 Through Scratchpad 7 Registers (Sheet 1 of 2)
  - These registers affect primary and secondary interrupts in the same way and are described
- 17516.9 PROM Registers
  - This section describes the six PROM registers. See Chapter8 for theory of operation information.
  - Table 107. Primary Expansion ROM BAR
  - Table 106. Scratchpad 0 Through Scratchpad 7 Registers (Sheet 2 of 2)
  - 176Table 108. Primary Expansion ROM Setup Register
  - 177Table 109. ROM Setup Register
  - Table 110. ROM Data Register
  - 178Table 111. ROM Address Register
  - Table 112. ROM Control Register (Sheet 1 of 2)
- 17916.10 SROM Registers
  - This sections describes the SROM registers. See Chapter 9 for theory of operation information.
  - Table 113. Mode Setting Configuration Register (Sheet 1 of 2)
  - I
  - Table 112. ROM Control Register (Sheet 2 of 2)
  - 180Table 114. Serial Preload Sequence (Sheet 1 of 3)
  - Table 113. Mode Setting Configuration Register (Sheet 2 of 2)
  - 181Table 114. Serial Preload Sequence (Sheet 2 of 3)
  - 182Table 114. Serial Preload Sequence (Sheet 3 of 3)
- 18316.11 Arbiter Control
- 16.12 Error Registers
  - Table 115. Arbiter Control Register
  - 184Table 116. Primary SERR# Disable Register
  - Table 117. Secondary SERR# Disable Register
- 18516.13 Init Registers
  - Table 117. Secondary SERR# Disable Register
  - Table 118. Power Management ECP ID and Next Pointer Register
  - 186Table 119. Power Management Capabilities Register
  - 187Table 120. Power Management Control and Status Register
  - Table 121. PMCSR Bridge Support Extensions
  - Table 122. Power Management Data Register
  - Table 123. Reset Control Register
  - 188
    - 189Table 124. CompactPCI Hot-Swap Capability Identifier and Next Pointer Register
    - Table 125. CompactPCI Hot-Swap Control Register (Sheet 1 of 2)
- 19016.14 JTAG Registers
  - Table 126. JTAG Instruction Register Options (Sheet 1 of 2)
  - Table 125. CompactPCI Hot-Swap Control Register (Sheet 2 of 2)
  - 191Table 126. JTAG Instruction Register Options (Sheet 2 of 2)
- 19216.15 VPD Registers
  - 193
195Acronyms A
197Index
- A
- B
- C
- D
- F
- I
- M
- N
- O
- P
- 198Q
- R
- S
- T
- U
- V
- W

Intel 21555 manuals

Intel 21555 User Manual

Intel 21555 Manual