Intel SA-1100 manuals
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388 pages 4.61 Mb
2 SA-1100 Developers Manual3 Contents21 Introduction29 Functional Description2.1 Block Diagram2-2 SA-1100 30 * ARM is a trademark and StrongARM is a registered trademark of ARM Limited. Intel StrongARM SA-1100 Processing Core System Control Module (SCM) Peripheral Control Module (PCM) SA-1100 Developers Manual 2-3 31 2.2 Inputs/OutputsFigure 2-2. SA-1100 Functional Diagram Intel StrongARM SA-1100 [208-pins] 32 2.3 Signal Description35 2.4 Memory Map37 ARM Implementation Options 43 Instruction Set4.1 Instruction Set 4.2 Instruction Timings 45 Coprocessors 55 Caches, Write Buffer, and Read Buffer6.1 Instruction Cache (Icache)6.1.1 Icache Operation 6.1.2 Icache Validity6.1.2.1 Software Icache Flush 6.1.3 Icache Enable/Disable and Reset6.1.3.1 Enabling the Icache 6.1.3.2 Disabling the Icache 56 6.2 Data Caches (Dcaches)59 6.3 Write Buffer (WB)6.3.1 Bufferable Bit 6.3.2 Write Buffer Operation6.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1) 6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0) 6.3.2.3 Unbufferable Writes (B=0) 6.3.3 Enabling the Write Buffer6.3.3.1 Disabling the Write Buffer 60 6.4 Read Buffer (RB)63 Memory-Management Unit (MMU)67 Clocks71 System Control Module115 Memory and PCMCIA Control Module151 Peripheral Control Module11.1 Read/Write Interface 152 11.2 Memory Organization154 11.3 Interrupts155 11.4 Peripheral Pins156 11.5 Use of the GPIO Pins for Alternate Functions157 11.6 DMA Controller166 11.7 LCD Controller206 11.8 Serial Port 0 USB Device Controller228 11.9 Serial Port 1 SDLC/UART253 11.10 Serial Port 2 Infrared Communications Port (ICP)278 11.11 Serial Port 3 - UART11.11.1 UART Operation 281 11.11.2 UART Register Definitions11.11.3 UART Control Register 0 284 11.11.4 UART Control Registers 1 and 211.11.4.1 Baud Rate Divisor (BRD) 285 11.11.5 UART Control Register 3287 11.11.6 UART Data Register289 11.11.7 UART Status Register 011.11.7.1 Transmit FIFO Service Request Flag (TFS) (read-only, maskable 11.11.7.2 Receive FIFO Service Request Flag (RFS) (read-only, maskable 290 11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt)11.11.7.4 Receiver Begin of Break Status (RBB) (read/write, nonmaskable 11.11.7.5 Receiver End of Break Status (REB) (read/write, nonmaskable 11.11.7.6 Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt) 292 11.11.8 UART Status Register 111.11.8.1 Transmitter Busy Flag (TBY) (read-only, noninterruptible) 11.11.8.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) 11.11.8.3 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) 11.11.8.4 Parity Error Flag (PRE) (read-only, noninterruptible) 293 11.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible)11.11.8.6 Receiver Overrun Flag (ROR) (read-only, noninterruptible) 11.11.9 UART Register Locations 295 11.12 Serial Port 4 MCP / SSP296 11.12.1 MCP Operation302 11.12.2 MCP Register Definitions11.12.3 MCP Control Register 308 11.12.4 MCP Control Register 111.12.4.1 Clock Frequency Select (CFS) 11.12.5 MCP Data Registers 313 11.12.6 MCP Status Register11.12.6.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, 11.12.6.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable 316 11.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, noninterruptible)11.12.6.13 Codec Write Completed Flag (CWC) (read-only, noninterruptible) 11.12.6.14 Codec Read Completed Flag (CRC) (read-only, noninterruptible) 11.12.6.15 Audio Codec Enabled Flag (ACE) (read-only, noninterruptible) 11.12.6.16 Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible) 319 11.12.7 SSP Operation11.12.7.1 Frame Format 323 11.12.7.2 Baud Rate Generation11.12.7.3 SSP Transmit and Receive FIFOs 11.12.7.4 CPU and DMA Register Access Sizes 11.12.7.5 Alternate SSP Pin Assignment 324 11.12.8 SSP Register Definitions11.12.9 SSP Control Register 0 327 11.12.10 SSP Control Register 1330 11.12.11 SSP Data Register 331 11.12.12 SSP Status Register11.12.12.1 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) 11.12.12.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) 11.12.12.3 SSP Busy Flag (BSY) (read-only, noninterruptible) 11.12.12.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable 332 11.12.12.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable 11.12.12.6 Receiver Overrun Status (ROR) (read/write, nonmaskable interrupt)SA-1100 Developers Manual 11-183 333 11.12.13 MCP Register Locations11.12.14 SSP Register LocationsTable 11-19. MCP Control, Data, and Status Register Locations Table 11-20. SSP Control, Data, and Status Register Locations 334 11.13 Peripheral Pin Controller (PPC)345 DC Parameters349 AC Parameters355 Package and PinoutSA-1100 Developers Manual 14-1 14.1 Mechanical Data and Packaging Information 357 14.2 Mini-Ball Grid Array (mBGA)SIDE VIEW TOP VIEW256 SOLDER BALLS 12345678 1345678 C B A D C B A Figure 14-2 Table14-2 359 Debug Support15.1 Instruction Breakpoint 15.2 Data Breakpoint 361 Boundary-Scan Test Interface371 Register Summary A377 3.6864MHz Oscillator Specifications BB.1 SpecificationsB.1.1 System Specifications3.6864MHz Oscillator Specifications 378 B.1.1.1. Parasitic Capacitance Off-chip Between PXTAL and PEXTALB.1.1.2. Parasitic Capacitance Off-chip Between PXTAL or PEXTAL and VSS B.1.1.3. Parasitic Resistance Between PXTAL and PEXTAL B.1.1.4. Parasitic Resistance Between PXTAL or PEXTAL and VSSSA-1110 Developers Manual B-3 3.6864MHz Oscillator Specifications 379 B.1.2 Quartz Crystal SpecificationThe following specifications for the quartz crystal are shown in the figure and table below. Co Q1 Q2 Cm Lm Rm 381 32.768kHz Oscillator Specifications CC.1 SpecificationsC.1.1 System SpecificationsC.1.1.1. Temperature Range C.1.1.2. Current Consumption C.1.1.3. Startup Time 382 C.1.1.4. Frequency Shift Due to Temperature Effect on the CircuitC.1.1.5. Parasitic Capacitance Off-chip Between TXTAL and TEXTAL C.1.1.6. Parasitic Capacitance Off-chip Between TXTAL or TEXTAL and VSS C.1.1.7. Parasitic Resistance Between TXTAL and TEXTAL C.1.1.8. Parasitic Resistance Between TXTAL or TEXTAL and VSSSA-1100 Developers Manual C-3 383 C.1.2 Quartz Crystal SpecificationThe following specifications for the quartz crystal are shown in the figure and table below. CoSpecification Minimum Typical Maximum Unit Q1 Q2 Cm Lm RmSA-1100 Developers Manual D-1 Internal Test 385 Internal Test DD.1 Test Unit Control Register (TUCR)
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