External Logic for Pcmcia Implementation, 10-28 | Intel SA-1100

Memory and PCMCIA Control Module

10.6.2External Logic for PCMCIA Implementation

The SA-1100 requires external logic to complete the PCMCIA socket interface. Figure 10-12and Figure 10-13show general solutions for a one- and two-socket configuration. Figure 10-14shows a solution for the voltage-control circuit. These diagrams provide the logical connections necessary for support of 3 V and 5 V PCMCIA cards as well as hot insertion capability. For dual-voltage support, level shifting buffers are required for all signals. Hot insertion capability requires that each socket be electrically isolated from the other. If one or both of these features is not required, then some of the logic shown in these diagrams may be eliminated.

The pull-ups shown are included for compliance with the PCCARD xxx standard. Low power systems should remove power from these pull-ups during sleep to avoid unnecessary power consumption. The CD<2:1> signals have been “ORed” before being provided to the SA-1100. This signal is then routed into a GPIO pin for interrupt capability. Similarly, RDY/BSY is routed to a GPIO. The INPACK# signal is not used. In the data bus transceiver control logic, nCE1 should control the enable for the low byte lane and nCE2 should control the enable for the high byte lane.

10-28

SA-1100 Developer’s Manual

Image 142

Intel SA-1100 manual External Logic for Pcmcia Implementation, 10-28

Contents

Intel StrongARM SA-1100 Microprocessor Developer’s Manual SA-1100 Developer’s Manual Contents Caches, Write Buffer, and Read Buffer Memory-Management Unit MMU 1.6 System Control Module Reviving the DRAMs from Self-Refresh Mode Memory and Pcmcia Control Module Peripheral Control Module 11-39 11.8.3.4Endpoint 0 Interrupt Mask EIM 11-64 11.8.3.5Receive 11-81 SA-1100 Developer’s Manual 11-128 Serial Port 4 MCP / SSP 11-169 11.12.12.1Transmit Fifo Not Full Flag TNF KHz Oscillator Specifications Register Summary MHz Oscillator SpecificationsInternal Test Figures SA-1100 Power and Clock Supply Sources and States Tables 14-4 Page LCD IntroductionIntel StrongARM SA-1100 Microprocessor DMA Features of the SA-1100 CPU for AA and EA Parts Features of the SA-1100 CPU for CA and DA Parts Additional Features Built into SA-1100 Chipset Changes to the SA-1100 Core from the SA-110 Overview Example System SA-1100 Example System ARM Architecture Write Buffer Read BufferPage Block Diagram Functional Description SA-1100 Block Diagram Inputs/Outputs Signal Descriptions Sheet 1 Signal DescriptionName Type Description Signal Descriptions Sheet 2 VDD Signal Descriptions Sheet 3TDO OCZ VSS Memory Map 1GB Pcmcia Interface Mbyte Static Memory ROM, Flash, Sram Big and Little Endian ARM Implementation OptionsExceptions Power-Up Reset ROM Size Select Abort Exception Priorities Address Exception Mode on EntryVector Summary Vector Summary Interrupt Latencies and Enable Timing CoprocessorsPage Instruction Set Instruction Group Result Delay Issue CyclesInstruction Set Instruction TimingsPage Coprocessors Internal Coprocessor Instructions Cache and MMU Control Registers Coprocessor Coprocessor 15 DefinitionRegister 0 ID Register Register Reads Register Writes Register 1 Control Register 6 Fault Address Register 3 Domain Access ControlRegister 5 Fault Status Register 2 Translation Table Base Function Register 7 Cache Control OperationsRegister 8 TLB Operations OPC2 Register 9 Read-Buffer Operations Registers 10 12 Reserved Register 13 Process ID Virtual Address Mapping Access process ID register 0b000 0b0000CRm Register 14 Debug Support Breakpoints Dbcr Bit Action Register 15 Test, Clock, and Idle Control 0b010 0b0100 Wait for interrupt 0b1000Page Icache Operation Caches, Write Buffer, and Read BufferInstruction Cache Icache Icache Validity Enabling the Icache Icache Enable/Disable and ResetData Caches Dcaches Disabling the Icache Cacheable Reads C = Cacheable Bit CBufferable Bit B Noncacheable Reads C = Software Dcache Flush Dcaches Enable/Disable and ResetDoubly Mapped Space Bufferable Bit Write Buffer WBWrite Buffer Operation Writes to a Bufferable and Noncacheable Location B=1,C=0 Read Buffer RBEnabling the Write Buffer Unbufferable Writes B=0 Caches, Write Buffer, and Read Buffer Page Data Aborts MMU Faults and CPU AbortsMemory-Management Unit MMU MMU Registers Buffered Writes Interaction of the MMU, Icache, Dcache, and Write BufferCacheable Reads Linefetches Valid MMU, Dcache, and Write Buffer Combinations To disable the MMU Mini Data CachePage RTC ClocksSA-1100 Crystal Oscillators ARM Core Clock Configurations Core Clock Configuration RegisterRestrictions on Changing the Core Clock Configuration CCF40 Core Clock Frequency in MHz MHz Crystal Oscillator Driving SA-1100 Crystal Pins from an External Source Clocking During Test System Control Module General-Purpose I/O Gpio Register Definitions Gpio Pin Edge Detect Gpio Pin-Level Register Gplr Bit Name Description Bit Reset Gpio Pin Direction Register Gpdr PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Bit Name Description Gpio Falling-Edge Detect Register Grer Bit Name Description Gpio Rising-Edge Detect Register Grer31..28 Reserved Gpio Edge Detect Status Register Gedr Gpio Alternate Function Register Gafr Pin Alternate Function Direction Unit Signal Description Gpio Alternate Functions Gpio Register Locations Address Name Description Interrupt Bits Interrupt ControllerInterrupt Controller Register Definitions Interrupt Bit Position Unit Source Module Interrupt Controller Pending Register IcprBit Field Description IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 IMn Interrupt mask n where n = 0 through Interrupt Controller Mask Register Icmr Interrupt Controller Level Register Iclr Bit Name Interrupt Controller Control Register Iccr Disable idle maskIdle mode. This bit is cleared during all resets DIM Interrupt Controller Register Locations Real-Time ClockRTC Counter Register Rcnr ALE RTC Alarm Register RtarRTC Status Register Rtsr HZE RTC Trim Register Rttr Trim ProcedureOscillator Frequency Calibration Rttr Value Calculations Trim Example #1 Measured Value Has No Fractional Component Operating System Timer Real-Time Clock Register Locations OS Timer Watchdog Match Enable Register Ower OS Timer Count Register OscrOS Timer Match Registers 0-3 OSMR0, OSMR1, OSMR2, OSMR3 WME OS Timer Status Register Ossr Watchdog Timer OS Timer Interrupt Enable Register OierInterrupt enable channel OS Timer Register Locations OS Timer Register Locations Idle Mode Power ManagerRun Mode Entering Idle Mode CPU Preparation for Sleep Mode Sleep ModeExiting Idle Mode Events Causing Entry into Sleep Mode Sleep Shutdown Sequence During Sleep ModeSleep Wake-Up Sequence Booting After Sleep Mode Assumed Behavior of an SA-1100 System in Sleep Mode Reviving the DRAMs from Self-Refresh Mode RUN Hardware ResetIdle Sleep Pin State During Step Pin Operation in Sleep ModePin Name Type Power Manager Registers Power Manager Control Register Pmcr Power Manager General Configuration Register Pcfr Opde Power Manager PLL Configuration Register Ppcr Power Manager Wake-Up Enable Register Pwer WEn BFS Power Manager Sleep Status Register PssrVFS Peripheral control hold Bit is cleared. This bit is cleared on hardware resetDram control hold 31..5 Reserved Power Manager Scratch Pad Register Pspr Power Manager Gpio Sleep State Register Pgsr Power Manager Oscillator Status Register Posr Power Manager Register LocationsPower Manager Register Locations Reset Controller Hardware reset Software reset Reset Controller RegistersReset Controller Software Reset Register Rsrr SWR Reset Controller Status Register Rcsr Reset Controller Register LocationsReset Controller Register Locations Page Intel Memory and Pcmcia Control ModuleOverview of Operation SA-1100 Memory Controller Interface Memory and Pcmcia Control Module 10-2 Example Memory Configuration Example Memory System Writes Types of Memory AccessesReads Transaction Summary SA-1100 Transactions Read-Lock-WriteAborts and Nonexistent Memory Bus Operation Physical Address Symbol Register Name Memory Configuration RegistersMemory Interface Control Registers Dram Configuration Register Mdcnfg CDB2 Mem clock frequency /4 31..17 DRI140 Dram refresh intervalCycle Will not be interrupted Dram CAS Waveform Shift Registers MDCAS0, MDCAS1, MDCAS2 Static Memory Control Registers MSC1-0 ROM or the first access of a burst ROMFor Flash and SRAM, this determines the read access time One memory clock cycle is added to this value Accesses of a burst ROM 12..8 RDNx40 ROM delay next accessFor Flash and SRAM, this determines the write pulse width Expansion Memory Pcmcia Configuration Register Mecr Bclksel BSxx Bit EncodingBclk Speeds for 160-MHz Processor Core Frequency Bclk Cycle Time-ns Dram Memory Size Options Dynamic Interface OperationDram Overview Dram Row/Column Address Multiplexing Dram Timing Addr Mdcnfgtrp = 4 MDCNFGCDB2 = Dram Burst-of-Eight Transactions Dram Refresh Dram Self-Refresh in Sleep ModeStatic Memory Interface 10-18 ROM Timing Diagrams and Parameters ROM Interface Overview Input Data Latch A255A42 10-20 Eight Beat Burst Read from Burst-of-Four ROM SA-1100 Developer’s Manual Sram Write Timing Diagram 4-Beat Burst Sram Timing Diagrams and ParametersSram Interface Overview Flash Eprom Interface Overview Flash Eprom Timing Diagrams and Parameters 10-24 Dram Access Followed by a Refresh Operation Static Access Followed by a Dram AccessDram Access Followed by a Static Access General Memory BUS Timing Pcmcia Overview 10-26 10.6.1 32-Bit Data Bus Operation Address External Logic for Pcmcia Implementation 10-28 12. Pcmcia External Logic for a Two-Socket Configuration 13. Pcmcia External Logic for a One-Socket Configuration 10-30 Pcmcia Interface Timing Diagrams and Parameters 14. Pcmcia Voltage-Control Logic 15. Pcmcia Memory or I/O 16-Bit Access 10-32 16. Pcmcia I/O 16-Bit Access to 8-Bit Device Initialization of the Memory Interface Flow of Events After Reset or Exiting Sleep Mode10-34 Alternate Memory Bus Master Mode Page Peripheral Control Module Read/Write Interface Memory Organization Peripheral Register Width DMA Burst Size LCD Controller 0h B010 Serial Port Peripheral Units’ Base AddressesPeripheral Serial Protocol Base Address ICP Hssp Interrupt InterruptsPeripheral Units’ Interrupt Numbers Peripheral Dedicated Peripheral Pins Peripheral PinsPeripheral Gpio Pin Function Use of the Gpio Pins for Alternate Functions Peripheral Unit Gpio Pin Assignment DMA Controller DMA Register Definitions DMA Device Address Register DDARn Controller From Half-word wide D31 D0 1 0 from memoryDevice From To Half-word wide To From Byte-wide Ddar Fields Unit Name Function Address DA318 DS30 Valid Settings for the DDARn Register11-10 DMA Control/Status Register DCSRn DMA Buffer a Start Address Register DBSAn DMA Buffer a Transfer Count Register DBTAn DMA Buffer B Transfer Count Register DBTBn DMA OperationDMA Buffer B Start Address Register DBSBn TCB120 Transfer count buffer B Physical Address Register Name Symbol DMA Register List DBSB3 DBSA3DBTA3 DBTB3 LCD Controller 11-16 Lpclk Frame Buffer LCD Controller OperationDMA to Memory Interface 11-18 PBS To palette 13..12Pixel bit size Frame to palette Unused Red Data30 Green Data30 Blue Data30 Encoded Pixel Data70 BitEncoded Pixel Data150 FrameBufferSize = 32 + 16 + è 11-22 Input Fifo Lookup Palette Color/Gray-Scale Intensities and Modulation Rates Color/Gray-Scale DitheringOutput Fifo Dither Value Intensity Modulation Rate LCD Controller Pins LCD Controller Register Definitions Color/Monochrome Select CMS LCD Enable LENLCD Controller Control Register Single-/Dual-Panel Select SDS LCD Controller Data Pin Utilization Single Passive Screen Portion PinsDual Panel Active Panel LCD Data-Pin Pixel Ordering 11-28 Error Interrupt Mask ERM LCD Disable Done Interrupt Mask LDMBase Address Update Interrupt Mask BAM Passive/Active Display Select PAS 11-30 Palette DMA Request Delay PDD Double-Pixel Data DPD Pin Mode11.7.3.8 Big/Little Endian Select BLE SDS LENCMS LDM DPD PASBLE PDD End-of-Line Pixel Clock Wait Count ELW Pixels Per Line PPLHorizontal Sync Pulse Width HSW 11-34 HSW Beginning-of-Line Pixel Clock Wait Count BLWPPL ELW Vertical Sync Pulse Width VSW Lines Per Panel LPP11-36 End-of-Frame Line Clock Wait Count EFW Beginning-of-Frame Line Clock Wait Count BFW EFW LPPVSW BFW Pixel Clock Divider PCD AC Bias Pin Frequency ACB Horizontal Sync Polarity HSP AC Bias Pin Transitions Per Interrupt APIVertical Sync Polarity VSP Pixel Clock Polarity PCP Output Enable Polarity OEP Address 0h B010 PCP LCD Controller DMA RegistersHSP OEP DBAR1 DMA Channel 1 Base Address Register31..0 DMA channel 1 base address pointer DMA channel 1 current address pointer DMA Channel 1 Current Address RegisterDCAR1 Equal to the calculated end address of the buffer DCAR2 DMA Channel 2 Base and Current Address RegistersDBAR2 DMA channel 2 current address pointer Bus Error Status BER read/write, maskable interrupt LCD Disable Done Flag LDD read/write, maskable interruptBase Address Update Flag BAU read-only, maskable interrupt LCD Controller Status Register AC Bias Count Status ABC read/write, nonmaskable interrupt LDD BAU IOL BERABC IUL LCD Controller Register Locations LCD Controller Control, DMA, and Status Register Locations LCD Controller Pin Timing Diagrams LDDx0 LDDx0 Lfclk Llclk Lpclk11-52 12. Passive Mode Pixel Clock and Data Pin Timing DPD = 13. Active Mode Timing 11-54 14. Active Mode Pixel Clock and Data Pin Timing USB Operation Serial Port 0 USB Device Controller11-56 Bus State UDC+/UDC- Pin Levels Signalling Levels10. USB Bus States Port Bit Value Digital Data Nrzi Data Bit Encoding11-58 Endpoint Field Value UDC Endpoint Selected Field Formats11. Endpoint Field Addressing Endpoint CRC5 Packet FormatsPID CRC16 OUT Transaction FormatsAction Packets from UDC to host are boldface Action Token Packet Data Packet Setup DATA0UDC Device Requests 11-62 12. Host Device Request Summary UDC Register DefinitionsRequest Name UDC Control Register Address 0h 8000 Reset Interrupt Mask REMSuspend/Resume Interrupt Mask SRM Udccr Udcar UDC Address RegisterUDC OUT Max Packet Register Udcomp Address 0h 8000 000C UDC in Max Packet RegisterUdcimp UDC Endpoint 0 Control/Status Register SSE FST SST IPR OPR Serviced Setup End SSEUDCCS0 SSE UDC Endpoint 1 Control/Status Register Receive Fifo Service RFSReceive Packet Error RPE Receive Packet Complete RPC RNE FST SST RPE RPC RFS Bits 7..6 ReservedUDCCS1 RNE UDC Endpoint 2 Control/Status Register Transmit Fifo Service TFSTransmit Packet Error TPE Transmit Packet Complete TPC UDCCS2 FST SST TUR TPE TPC TFS UDCD0 UDC Endpoint 0 Data RegisterUDC Endpoint 0 Write Count Register Data Top/bottom of transmit/receive Fifo data UDC Data RegisterUddr Read Bottom of receive Fifo data UDC Status/Interrupt Register Rstir Resir Susir TIR RIR EIR Reset Interrupt Request RstirUdcsr Rstir UDC Register Locations Serial Port 1 SDLC/UART13. UDC Control, Data, and Status Register Locations Sdlc Operation Control Field Frame FormatAddress Field CRC-CCITT CRC Field Data FieldBaud Rate Generation Receive Operation 11-82 Transmit Operation Simultaneous Use of the Uart and Sdlc Transmit and Receive FIFOs CPU and DMA Register Access SizesSdlc Register Definitions 11-84 SDLC/UART Select SUS Loopback Mode LBMSdlc Control Register Single/Double Flag Select SDF Sample Clock Direction SCD Sample Clock Enable SCEBit Modulation Select BMS 11-86 Address 0h 8002 Receive Clock Edge Select RCETransmit Clock Edge Select TCE SDCR0 Abort After Frame AAF TCE Receive Fifo Interrupt Enable RIE Transmit Enable TXEReceive Enable RXE Transmit Fifo Interrupt Enable TIE Transmit Fifo Underrun Select TUS Address Match Enable AMEReceiver Abort Interrupt EnableRAE 11-90 RAE TUS AME TIE RIE RXE TXE AAF SDCR1Read/Write RAE SDCR2 Address Match Value AMVAMV Address 0h 8002 006C Sdlc Control Registers 3Baud Rate Divisor BRD SDCR3 Sdlc Data Register 11-94 ROR CRE EOF Address 0h 0078Sddr ROR Receiver Abort Status RAB read/write, maskable interrupt Sdlc Status RegisterTransmit Underrun Status TUR read/write, maskable interrupt 11-96 SA-1100 Developer’s Manual 11-97 SDSR0 RFS TFS RAB TUR EIF Receive Fifo Not Empty Flag RNE read-only, noninterruptible Receiver Synchronized Flag RSY read-only, noninterruptibleTransmitter Busy Flag TBY read-only, noninterruptible Transmit Fifo Not Full Flag TNF read-only, noninterruptible Receiver Overrun Status ROR read-only, noninterruptible CRC Error Status CRE read-only, noninterruptible11-100 RSY SDSR1ROR CRE EOF RTD TNF RNE TBY Uart Register Locations 14. Uart Control, Data, and Status Register Locations Sdlc Register Locations Serial Port 2 Infrared Communications Port ICP15. Sdlc Control, Data, and Status Register Locations Uart Frame Format Low-Speed ICP OperationHP-SIR*Modulation 11-104 11.10.2.1 4PPM Modulation High-Speed ICP OperationChip Timeslots Data = Hssp Frame Format SA-1100 Developer’s Manual 11-107 11-108 SA-1100 Developer’s Manual 11-109 11-110 Uart Register Definition HP-SIR Enable HSELow-Power Mode LPM Uart Control Register IrDA Transmission Rate ITR Hssp Register DefinitionsHssp Control Register LPM SA-1100 Developer’s Manual 11-113 11-114 HSCR0 Address 0h 8004AME TIM RIM RXE TXE TUS LBM ITR Search for the next preamble HSCR111-116 Transmit Pin Polarity Select TXP Receive Pin Polarity Select RXP RXP TXP 0h 9006HSCR2 RXP Hssp Data Register Last Fifo entry is transferred to the ROR bit Address 0h 8004 006CHsdr HSSR1 Hssp Status Register Receiver Abort Status RAB read/write, nonmaskable interrupt 11-122 FRE RFS TFS RAB TUR EIF Framing Error Status FRE read/write, nonmaskable interruptHSSR0 FRE End-of-Frame Flag EOF read-only, noninterruptible 11-124 SA-1100 Developer’s Manual 11-125 HSSR1 ROR CRE EOF TNF RNE TBY RSY 16. Uart Control, Data, and Status Register Locations Hssp Register Locations17. Hssp Control, Data, and Status Register Locations LSB MSB Serial Port 3 UartUart Operation 11-128 30. NRZ Bit Encoding Example 0100 11-130 Uart Register Definitions Parity Enable PE11.11.3.2 Odd/Even Parity Select OES Data Size Select DSS Stop Bit Select SBS11-132 UTCR0 TCE RCE SCE DSS SBS OES UTCR1 Bit Reset BRD70Uart Control Registers 1 UTCR2 Transmitter Enable TXE Receiver Enable RXEBreak BRK UTCR3 LBM TIE RIE BRK TXE RXE Uart Data Register Utdr ROR FRE PRE Uart Status Register Receiver Idle Status RID read/write, maskable interrupt Error in Fifo Flag EIF read-only, nonmaskable interrupt11-140 UTSR0 Address 0h 8005 001CEIF REB RBB RID RFS TFS Parity Error Flag PRE read-only, noninterruptible 11-142 Framing Error Flag FRE read-only, noninterruptible Receiver Overrun Flag ROR read-only, noninterruptible Read-Only UTSR1ROR FRE PRE TNF RNE TBY Serial Port 4 MCP / SSP MCP Operation 11-146 31. MCP Frame Data Format Audio and Telecom Sample Rates and Data Transfer 11-148 MCP Transmit and Receive Fifo Operation Bit Audio Data Telecom Data Codec Control Register Data Transfer11-150 External Clock Operation Alternate SSP Pin Assignment Audio Sample Rate Divisor ASD MCP Register DefinitionsMCP Control Register 11-152 Telecom Sample Rate Divisor TSD External Clock Select ECS Multimedia Communications Port Enable MCE11.12.3.5 A/D Sampling Mode ADM 11-154 Audio Transmit Fifo Interrupt Enable ATE Telecom Transmit Fifo Interrupt Enable TTETelecom Receive Fifo Interrupt Enable TRE Audio Receive Fifo Interrupt Enable are Audio sample rate divisor External Clock Prescaler ECPASD TSD ADM MCEECS TTE Clock Frequency Select CFS MCP Data RegistersCFS Reserved for future enhancements MCP Data RegisterAddress 0h 8006 MCP Data Register 0 MCDR0 Read/Write 15..4 Address 0h 8006 000C MCP Data Register 1 MCDR1 Read/Write SA-1100 Developer’s Manual 11-161 15..0 Codec Reg Address R/W Reset BitAddress 0h 8006 MCP Data Register 2 MCDR2 Read/Write Register read Read/write Read Returns a zero MCP Status Register 11-164 SA-1100 Developer’s Manual 11-165 Codec Write Completed Flag CWC read-only, noninterruptible Audio Codec Enabled Flag ACE read-only, noninterruptibleTelecom Codec Enabled Flag TCE read-only, noninterruptible Codec Read Completed Flag CRC read-only, noninterruptible TTS ATSARS TRS ANF TTUTRO ANE SSP Operation 35. Texas Instruments* Synchronous Serial Frame Format 11-170 36. Motorola* SPI Frame Format 37. National Microwire* Frame Format 11-172 SSP Transmit and Receive FIFOs Bit Bit Data SSP Control Register SSP Register Definitions11-174 Synchronous Serial Port Enable SSE Frame Format FRF FRF Serial Clock Rate SCRSCR Serial Clock Polarity SPO LSB Serial Clock Phase SPHSclk SPO=0 Sclk SPO=1 Sfrm TXD4 RXD4 11-178 SPO Address 0h 8007 006C SSP Data RegisterJustifies data and zero fills unused bits 11-180 SSP Status Register SSP Busy Flag BSY read-only, noninterruptible BSY 19. MCP Control, Data, and Status Register Locations MCP Register LocationsSSP Register Locations 20. SSP Control, Data, and Status Register Locations PPC Operation Peripheral Pin Controller PPC11-184 PPC Register Definitions PPC Pin Direction Register Sclk PPC Pin State Register Address 0h 9006 Ppsr PPC Pin StateRegister Read/Write LCD line clock pin state LCD pixel clock pin stateRead Current state of LCD pixel clock pin returned Read Current state of LCD line clock pin returned SSP Pin Reassignment SPR PPC Pin Assignment RegisterUart Pin Reassignment UPR UPR PPC Sleep Mode Pin Direction Register 11-190 LCD line clock sleep mode pin direction LCD pixel clock sleep mode pin directionLCD pixel clock pin configured as input during sleep LCD line clock pin configured as input during sleep PPC Pin Flag Register PPC Register Locations 21. PPC Control and Flag Register LocationsPage Absolute Maximum Ratings Symbol Parameter Min Max UnitsDC Parameters SA-1100 DC Maximum Ratings SA-1100 DC Operating Conditions Symbol Parameter Min Nom Max UnitsDC Operating Conditions × Vddx VDD Power Supply Voltages and CurrentsParameter SA-1100 Units VddxPage Test Conditions AC ParametersSA-1100 Output Derating Memory Bus Memory Bus Out Memory Bus and Pcmcia Signal TimingsModule Considerations 13-2 MCP Signals LCD Controller SignalsLLDD70 fall SA-1100 AC Timing Table for AA and BA Parts Pin Name Symbol Parameter Min Max UnitTiming Parameters Sfrmc Asynchronous Signal Timing Descriptions Page Package and Pinout Mechanical Data and Packaging Information SA-1100 Pinout 208-Pin Quad Flat Pack 14-2 Mini-Ball Grid Array mBGA SA-1100 256 Mini-Ball Grid Array Mechanical Drawing SA-1100 Pinout 256-Pin Mini-Ball Grid Array 14-4 Instruction Breakpoint Debug SupportData Breakpoint Page Test Access Port TAP Controller State Transitions Boundary-Scan Test Interface Instruction Register ResetPull-Up Resistors Public Instructions SAMPLE/PRELOAD ExtestClamp Bypass HighzIdcode 16-4 Test Data Registers Bypass Register 16.6.3 SA-1100 Boundary-Scan BS Register 16.6.2 SA-1100 Device Identification ID Code Register16-6 Tbsis Tbsih Boundary-Scan Interface SignalsTbscl Tbsch Tbsoh Tbsod Data Tbsss Tbssh Data Out Tbsdh Tbsdd Tbsr TbsoeData Out Tbsde Tbsrs Tbsrh Symbol Parameter Minimum Typical Maximum Units SA-1100 Boundary-Scan Interface TimingPage Register Summary Tucr B000 0048 Write ones to clear 004C Read only 0050 B000 0044DMA control/status register 2 write ones to set B000 0054 Ucdomp 8003 Reserved 8003 001C Sdlc Registers Serial Port 80028031 8004 007C 0h 8004 Ffff Reserved 8007 0078 0h 8007 Ffff Reserved PPC Registers 9006 Uart Registers Serial Port 80059006 0034 0h 9006 Ffff Reserved Specifications MHz Oscillator Specifications BSystem Specifications MHz Oscillator Specifications Specification Minimum Typical Maximum Unit Specification Quartz Crystal SpecificationTypical Maximum Unit Page Current Consumption KHz Oscillator Specifications CTemperature Range Startup Time Parasitic Resistance Between Txtal and Textal Frequency Shift Due to Temperature Effect on the CircuitParasitic Capacitance Off-chip Between Txtal and Textal Parasitic Resistance Between Txtal or Textal and VSS Corresponding to specified range of Rm are supplied Other providers supply a Quality Factor, Q, instead of RmTherefore, the values for Q Following table KHz Oscillator Specifications Test Unit Control Register Tucr Internal TestPMD TSEL2-0 TSEL2 TSEL1 TSEL0Page Support, Products, and Documentation