Intel SA-1100 ARM, Implementation Options

SA-1100 Developer’s Manual 3-1
ARM ™ Implementation Options 3
The following sections describe ARM™ architecture options that are implemented by the
Intel® StrongARM® SA-1100 Microprocessor (SA-1100).
3.1 Big and Little Endian
The big endian bit in the control register sets whether the SA-1100 treats words stored in memory
as being stored in big endian or little endian format. Memory is viewed as a linear collection of
bytes numbered upwards from 0. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 hold the
second, and so on.
In the little endian scheme, the lowest numbered byte in a word is considered to be the least
significant byte of the word and the highest numbered byte is the most significant. Byte 0 of the
memory system should be connected to data lines 7 through 0 (D<7:0>) in this scheme.
In the big endian scheme, the most significant byte of a word is stored at the lowest numbered byte
and the least significant byte is stored at the highest numbered byte. Therefore, byte 0 of the
memory system should be connected to data lines 31 through 24 (D<31:24>).
The state of the big endian bit changes the location of the bytes only within a 32-bit word. The
accessed bytes are changed for the load byte, store byte, load halfword, and store halfword
instructions only. Instruction fetches and word load and stores are not changed by the state of the
big endian bit, except when those accesses are performed with memory on 16-bit data busses. See
Chapter10 for details on configuring bus widths for various memory types.
These conventions are identical to those of the SA-110. In addition, the SA-1100 DMA controller
is programmable by channel as to the endian format of the transfer. For DMA transfers, all
memory accesses are words. Then the data is buffered and transferred to/from the device as
halfwords or bytes. When the words are assembled or disassembled, the endian format of the
channel is observed. For details on how DMA data is transferred relative to the endian format of
the channel, see the Section 11.6, “DMA Controller” on page 11-7 in Chapter 11, “Peripheral
Control Module”.
3.2 Exceptions
Exceptions arise whenever there is a need for the normal flow of program execution to be broken;
for example, so that the processor can be diverted to handle an interrupt from a peripheral. The
processor state just prior to handling the exception must be preserved so that the original program
resumes when the exception routine has completed. Many exceptions may arise at the same time.
The SA-1100 handles exceptions by making use of banked registers to save state. The contents of
PC and CPSR are copied into the appropriate R14 and SPSR, and the PC and mode bits in the
CPSR bits are forced to a value that depends on the exception. Interrupt disable flags are set where
required to prevent otherwise unmanageable nestings of exceptions. In the case of a reentrant
interrupt handler, R14 and the SPSR should be saved onto a stack in main memory before
reenabling the interrupt; when transferring the SPSR register to and from a stack, it is important to