Intel manual SA-1100 Pinout 256-Pin Mini-Ball Grid Array, 14-4

Package and Pinout

Table 14-2.

SA-1100 Pinout – 256-Pin Mini-Ball Grid Array

Pin

Signal

Type

BGA

Pin

Signal

Type

BGA

Pin

35

Type

BGA

Pin

Signal

Type

BGA

Pad

Pad

Pad

Pad

1

RXD_C

I/O

B1

65

GP[15]

I/O

N6

129

VSSX

–

G7

193

VDDX3

I

D7

2

TXD_C

I/O

C2

66

GP[14]

I/O

P6

130

VDDX2

–

L12

194

ROMSEL

I

D6

3

VDDX2

–

J13

67

VDDX1

–

D9

131

VSS

–

J16

195

TCK_BYP

I

A6

4

VSSX

–

A1

68

VSSX

–

F7

132

VDD

–

J14

196

TESTCLK

I

B6

5

VDD

–

C1

69

GP[13]

I/O

R6

133

nCS[3]

O

H14

197

TMS

I

C6

6

VSS

–

D3

70

GP[12]

I/O

R7

134

nCS[2]

O

H13

198

TCK

I

C5

7

D[0]

I/O

D2

71

GP[11]

I/O

T6

135

nCS[1]

O

H16

199

TDI

I

A5

8

D[8]

I/O

D1

72

GP[10]

I/O

P7

136

nCS[0]

O

H15

200

TDO

O

B5

9

D[16]

I/O

F4

73

GP[9]

I/O

T7

137

A[25]

O

G14

201

nTRST

I

B4

10

D[ 24]

I/O

E3

74

GP[8]

I/O

N8

138

A[24]

O

G16

202

BATT_FAULT

I

A4

11

D[ 1]

I/O

E2

75

GP[7]

I/O

P8

139

A[23]

O

G15

203

VSSX

–

H7

12

D[ 9]

I/O

E1

76

GP[6]

I/O

R8

140

A[22]

O

F15

204

VDDX1

–

E8

13

D[ 17]

I/O

F3

77

VDDX1

–

K10

141

VSSX

–

G8

205

VDD_FAULT

I

C4

14

D[25]

I/O

F2

78

VSSX

–

F8

142

VDDX2

–

L13

206

PWR_EN

O

A3

15

VDDX2

–

K5

79

VDD

–

T8

143

A[21]

O

F14

207

SFRM_C

O

B3

16

VSSX

–

B2

80

VSS

–

R9

144

A[20]

O

F13

208

SCLK_C

O

A2

17

D[2]

I/O

F1

81

GP[5]

I/O

P9

145

A[19]

O

F16

–

VSSX

–

H8

18

D[10]

I/O

G2

82

GP[4]

I/O

T9

146

A[18]

O

E15

–

VSSX

–

H9

19

D[18]

I/O

G3

83

GP[3]

I/O

N10

147

A[17]

O

E14

–

VSSX

–

H10

20

D[26]

I/O

H4

84

GP[2]

I/O

R10

148

A[16]

O

E16

–

VSSX

–

H11

21

D[3]

I/O

G1

85

GP[1]

I/O

P10

149

A[15]

O

D14

–

VSSX

–

J6

22

D[11]

I/O

H3

86

GP[0]

I/O

T10

150

A[14]

O

D15

–

VSSX

–

J7

23

D[19]

I/O

H2

87

L_BIAS

I/O

R11

151

VSS

–

D16

–

VSSX

–

J8

24

D[27]

I/O

J3

88

L_PCLK

I/O

P11

152

VDD

–

C15

–

VSSX

–

J9

25

VDD

–

H1

89

VDDX1

–

D11

153

VSSX

–

G9

–

VSSX

–

J10

26

VSS

–

J2

90

VSSX

–

F9

154

VDDX2

–

M5

–

VSSX

–

J11

27

VDDX2

–

D13

91

LDD0

I/O

N12

155

A[13]

O

C16

–

VSSX

–

K6

28

VSSX

–

C3

92

LDD1

I/O

T11

156

A[12]

O

B16

–

VSSX

–

K7

29

D[4]

I/O

J1

93

LDD2

I/O

R12

157

A[11]

O

C14

–

VSSX

–

K8

30

D[12]

I/O

K4

94

LDD3

I/O

P12

158

A[10]

O

B14

–

VSSX

–

K9

31

D[20]

I/O

K3

95

LDD4

I/O

P13

159

A[9]

O

B15

–

VSSX

–

L6

32

D[28]

I/O

K2

96

LDD5

I/O

T12

160

A[8]

O

A16

–

VSSX

–

L7

33

D[5]

I/O

K1

97

LDD6

I/O

R13

161

VSSX

–

G10

–

VSSX

–

L8

34

D[13]

I/O

L3

98

LDD7

I/O

T13

162

VDDX1

–

E6

–

VSSX

–

L9

35

D[21]

I/O

L2

99

VDDX1

–

K11

163

A[7]

O

A15

–

VDDX1

–

L11

36

D[29]

I/O

L1

100

VSSX

–

F10

164

A[6]

O

A14

–

VDDX1

–

E9

37

VDDX2

–

K12

101

L_LCLK

I/O

R14

165

A[5]

O

B13

–

VDDX1

–

E10

38

VSSX

–

D4

102

L_FCLK

I/O

T14

166

A[4]

O

C13

–

VDDX1

–

E11

39

D[6]

I/O

M4

103

nPOE

O

R15

167

A[3]

O

A13

–

VDDX1

–

M6

40

D[14]

I/O

M3

104

nPWE

O

T15

168

A[2]

O

B12

–

VDDX1

–

M7

41

D[22]

I/O

M2

105

nPIOR

O

P14

169

A[1]

O

C12

–

VDDX1

–

M8

42

D[30]

I/O

M1

106

nPIOW

O

P15

170

A[0]

O

D12

–

VDDX1

–

M9

43

D[7]

I/O

N3

107

VSSX

–

F11

171

VSSX

–

G11

–

VDDX1

–

M10

44

D[15]

I/O

N2

108

VDDX2

–

L4

172

VDDX1

–

E7

–

VDDX1

–

M11

45

D[23]

I/O

P3

109

VSS

–

T16

173

UDC-

I/O

A12

–

VDDX1

–

N7

46

D[31]

I/O

P2

110

VDD

–

R16

174

UDC+

I/O

C11

–

VDDX1

–

N9

47

VDD

–

N1

111

PSKTSEL

O

P16

175

RXD_1

I/O

B11

–

VDDX1

–

N11

48

VSS

–

P1

112

nIOIS16

I

N15

176

TXD_1

I/O

A11

–

VDDX2

–

E12

49

VDDX2

–

E4

113

nPWAIT

I

N16

177

RXD_2

I/O

B10

–

VDDX2

–

E13

50

VSSX

–

E5

114

nPREG

O

N14

178

TXD_2

I/O

D10

–

VDDX2

–

F5

51

GP[27]

I/O

R1

115

nPCE2

O

M13

179

RXD_3

I/O

C10

–

VDDX2

–

F12

52

GP[26]

I/O

T1

116

nPCE1

O

M15

180

TXD_3

I/O

A10

–

VDDX2

–

G4

53

GP[25]

I/O

R2

117

nWE

O

M14

181

VSSX

–

H6

–

VDDX2

–

G5

54

GP[24]

I/O

P4

118

nOE

O

M16

182

VDDX1

–

L10

–

VDDX2

–

G12

55

GP[23]

I/O

T2

119

VSSX

–

G6

183

VSS

–

A9

–

VDDX2

–

G13

56

GP[22]

I/O

R3

120

VDDX2

–

L5

184

TXTAL

I

B9

–

VDDX2

–

H5

57

VDDX1

–

D5

121

nRAS[3]

O

L15

185

TEXTAL

O

C9

–

VDDX2

–

H12

58

VSSX

–

F6

122

nRAS[2]

O

L14

186

PEXTAL

O

A8

–

VDDX2

–

J4

59

GP[21]

I/O

T3

123

nRAS[1]

O

L16

187

PXTAL

I

B8

–

VDDX2

–

J5

60

GP[20]

I/O

R4

124

nRAS[0]

O

K13

188

VDDP

–

C8

–

VDDX2

–

J12

61

GP[19]

I/O

T4

125

nCAS[3]

O

K15

189

VSS

–

D8

–

VDDX2

–

M12

62

GP[18]

I/O

P5

126

nCAS[2]

O

K14

190

VDD

–

A7

–

VDDX2

–

N4

63

GP[17]

I/O

R5

127

nCAS[1]

O

K16

191

nRESET

I

B7

–

VDDX2

–

N5

64

GP[16]

I/O

T5

128

nCAS[0]

O

J15

192

nRESET_OUT

O

C7

–

VDDX2

–

N13

Note: All VDDX1, VDDX2, and VDDX3 pins should be connected directly to the VDDX power plane of the system board. VDDP should be connected directly to the VDD plane of the system board.

14-4 SA-1100 Developer’s Manual