Memory and PCMCIA Control Module

Figure 10-16. PCMCIA I/O 16-Bit Access to 8-Bit Device

 

CPU Clock

 

 

Memory Clock

 

 

BS_xx+1

 

 

BCLK

 

 

A[25:1], nPREG,

 

 

PSKTSEL

 

 

 

BS_xx+1

2*(BS_xx+1)

 

 

A[0]

 

 

nPCE2

 

 

nPCE1

 

 

 

3*(BS_xx+1)

 

3*(BS_xx+1)

BS_xx+2

 

nPIOR, nPIOW

 

 

nIOIS16

 

 

nPWAIT

 

 

Latch Read

 

 

Data

 

 

Read Data

Low Byte

High Byte

D[7:0]

 

 

Write Data

Low Byte

High Byte

D[7:0]

 

 

BS_xx = 1

 

 

 

 

A4788-01

Timing parameters are in CPU clock cycle units. All are minimums except as noted:

Address access time: 6*(BS_xx+1)

Command (nPOE, nPWE, nPIOR, nPIOW) assertion time: 3*(BS_xx+1)

Address setup to command assert: 3*(BS_xx+1)

Address hold after command deassertion: BS_xx+1

nPWAIT valid after command assertion (max): 2*(BS_xx+1) -1

Chip enable (nPCE1,2) setup to nPOE, nPWE assert: 3*(BS_xx+1)

Chip enable (nPCE1,2) setup to nPIOR, nPIOW assert: 3*(BS_xx+1) - (nIOIS 16 delay from address)

Chip enabled hold from command deassert: BS_xx+1

See Chapter 13, “AC Parameters” for actual AC timing.

SA-1100 Developer’s Manual

10-33

Page 147
Image 147
Intel SA-1100 manual Pcmcia I/O 16-Bit Access to 8-Bit Device