Serviced Setup End SSE, UDCCS0, Sse Fst Sst Ipr Opr

Peripheral Control Module

11.8.7.8Serviced Setup End (SSE)

The serviced setup end bit will clear the SE bit (5) when writing a one.

	Address: 0h 8000 0010				UDCCS0			Read/Write
Bit	7		6	5	4	3	2	1		0

		SSE	SO	SE	DE	FST	SST		IPR	OPR

Reset	0		0	0	0	0	0	0		0

Bit	Name		Description

0	OPR	OUT packet ready (read-only).
		1	– OUT packet ready.

1	IPR	IN packet ready (read/write 1 to set).
		1	– IN packet ready.

2	SST	Sent stall (read/write 1 to clear).
		1	– UDC sent stall handshake.

3	FST	Force stall (read/write 1 to set).
		1	– Force stall handshake.

4	DE	Data end (read/write 1 to set).
		1	– The last byte of the data phase has been written.

5	SE	Setup end (read-only).
		1	– Control transfer ended before data end got set.

6	SO	Serviced OPR (write-only).
		1	– Clear OPR, bit 0.

7	SSE	Serviced setup end (write-only).
		1	– Clear SE, bit 5.

SA-1100 Developer’s Manual

11-69

Page 219

Image 219

Intel SA-1100 manual Serviced Setup End SSE, UDCCS0, Sse Fst Sst Ipr Opr

Contents

Developer’s Manual Intel StrongARM SA-1100 Microprocessor SA-1100 Developer’s Manual Contents Memory-Management Unit MMU Caches, Write Buffer, and Read Buffer System Control Module 1.6 Memory and Pcmcia Control Module Reviving the DRAMs from Self-Refresh Mode Peripheral Control Module 11-39 11.8.3.4Endpoint 0 Interrupt Mask EIM 11-64 11.8.3.5Receive 11-81 SA-1100 Developer’s Manual 11-128 Serial Port 4 MCP / SSP 11-169 11.12.12.1Transmit Fifo Not Full Flag TNF Register Summary MHz Oscillator Specifications KHz Oscillator SpecificationsInternal Test Figures Tables SA-1100 Power and Clock Supply Sources and States 14-4 Page DMA IntroductionIntel StrongARM SA-1100 Microprocessor LCD Features of the SA-1100 CPU for CA and DA Parts Features of the SA-1100 CPU for AA and EA Parts Changes to the SA-1100 Core from the SA-110 Additional Features Built into SA-1100 Chipset Overview SA-1100 Example System Example System ARM Architecture Read Buffer Write BufferPage Functional Description Block Diagram SA-1100 Block Diagram Inputs/Outputs Signal Description Signal Descriptions Sheet 1Name Type Description Signal Descriptions Sheet 2 VSS Signal Descriptions Sheet 3TDO OCZ VDD Memory Map Pcmcia Interface Mbyte Static Memory ROM, Flash, Sram 1GB ARM Implementation Options Big and Little EndianExceptions ROM Size Select Power-Up Reset Abort Vector Summary Address Exception Mode on EntryVector Summary Exception Priorities Coprocessors Interrupt Latencies and Enable TimingPage Instruction Timings Instruction Group Result Delay Issue CyclesInstruction Set Instruction SetPage Internal Coprocessor Instructions Coprocessors Register Register Reads Register Writes Coprocessor 15 DefinitionRegister 0 ID Cache and MMU Control Registers Coprocessor Register 1 Control Register 2 Translation Table Base Register 3 Domain Access ControlRegister 5 Fault Status Register 6 Fault Address OPC2 Register 7 Cache Control OperationsRegister 8 TLB Operations Function Registers 10 12 Reserved Register 9 Read-Buffer Operations Access process ID register 0b000 0b0000 Register 13 Process ID Virtual Address MappingCRm Dbcr Bit Action Register 14 Debug Support Breakpoints 0b010 0b0100 Wait for interrupt 0b1000 Register 15 Test, Clock, and Idle ControlPage Icache Validity Caches, Write Buffer, and Read BufferInstruction Cache Icache Icache Operation Disabling the Icache Icache Enable/Disable and ResetData Caches Dcaches Enabling the Icache Noncacheable Reads C = Cacheable Bit CBufferable Bit B Cacheable Reads C = Dcaches Enable/Disable and Reset Software Dcache FlushDoubly Mapped Space Write Buffer WB Bufferable BitWrite Buffer Operation Unbufferable Writes B=0 Read Buffer RBEnabling the Write Buffer Writes to a Bufferable and Noncacheable Location B=1,C=0 Caches, Write Buffer, and Read Buffer Page MMU Registers MMU Faults and CPU AbortsMemory-Management Unit MMU Data Aborts Valid MMU, Dcache, and Write Buffer Combinations Interaction of the MMU, Icache, Dcache, and Write BufferCacheable Reads Linefetches Buffered Writes Mini Data Cache To disable the MMUPage ARM ClocksSA-1100 Crystal Oscillators RTC CCF40 Core Clock Frequency in MHz MHz Crystal Oscillator Core Clock Configuration RegisterRestrictions on Changing the Core Clock Configuration Core Clock Configurations Driving SA-1100 Crystal Pins from an External Source Clocking During Test General-Purpose I/O System Control Module Gpio Pin Edge Detect Gpio Register Definitions Bit Name Description Gpio Pin-Level Register Gplr Gpio Pin Direction Register Gpdr Bit Reset PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Bit Name Description Gpio Rising-Edge Detect Register Grer Bit Name Description Gpio Falling-Edge Detect Register Grer31..28 Reserved Gpio Edge Detect Status Register Gedr Gpio Alternate Function Register Gafr Gpio Alternate Functions Pin Alternate Function Direction Unit Signal Description Address Name Description Gpio Register Locations Interrupt Interrupt ControllerInterrupt Controller Register Definitions Interrupt Bits Interrupt Controller Pending Register Icpr Bit Position Unit Source ModuleBit Field Description IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Interrupt Controller Mask Register Icmr IMn Interrupt mask n where n = 0 through Bit Name Interrupt Controller Level Register Iclr DIM Disable idle maskIdle mode. This bit is cleared during all resets Interrupt Controller Control Register Iccr Real-Time Clock Interrupt Controller Register LocationsRTC Counter Register Rcnr HZE RTC Alarm Register RtarRTC Status Register Rtsr ALE Trim Procedure RTC Trim Register RttrOscillator Frequency Calibration Trim Example #1 Measured Value Has No Fractional Component Rttr Value Calculations Real-Time Clock Register Locations Operating System Timer WME OS Timer Count Register OscrOS Timer Match Registers 0-3 OSMR0, OSMR1, OSMR2, OSMR3 OS Timer Watchdog Match Enable Register Ower OS Timer Status Register Ossr OS Timer Interrupt Enable Register Oier Watchdog TimerInterrupt enable channel OS Timer Register Locations OS Timer Register Locations Entering Idle Mode Power ManagerRun Mode Idle Mode Events Causing Entry into Sleep Mode Sleep ModeExiting Idle Mode CPU Preparation for Sleep Mode During Sleep Mode Sleep Shutdown SequenceSleep Wake-Up Sequence Booting After Sleep Mode Reviving the DRAMs from Self-Refresh Mode Assumed Behavior of an SA-1100 System in Sleep Mode Hardware Reset RUNIdle Sleep Pin Operation in Sleep Mode Pin State During StepPin Name Type Power Manager Control Register Pmcr Power Manager Registers Opde Power Manager General Configuration Register Pcfr Power Manager PLL Configuration Register Ppcr WEn Power Manager Wake-Up Enable Register Pwer Power Manager Sleep Status Register Pssr BFSVFS 31..5 Reserved Bit is cleared. This bit is cleared on hardware resetDram control hold Peripheral control hold Power Manager Gpio Sleep State Register Pgsr Power Manager Scratch Pad Register Pspr Power Manager Register Locations Power Manager Oscillator Status Register PosrPower Manager Register Locations Hardware reset Reset Controller SWR Reset Controller RegistersReset Controller Software Reset Register Rsrr Software reset Reset Controller Register Locations Reset Controller Status Register RcsrReset Controller Register Locations Page SA-1100 Memory Controller Interface Memory and Pcmcia Control ModuleOverview of Operation Intel 10-2 Memory and Pcmcia Control Module Example Memory System Example Memory Configuration Transaction Summary Types of Memory AccessesReads Writes Bus Operation Read-Lock-WriteAborts and Nonexistent Memory SA-1100 Transactions Memory Configuration Registers Physical Address Symbol Register NameMemory Interface Control Registers CDB2 Dram Configuration Register Mdcnfg Will not be interrupted 31..17 DRI140 Dram refresh intervalCycle Mem clock frequency /4 Dram CAS Waveform Shift Registers MDCAS0, MDCAS1, MDCAS2 One memory clock cycle is added to this value ROM or the first access of a burst ROMFor Flash and SRAM, this determines the read access time Static Memory Control Registers MSC1-0 12..8 RDNx40 ROM delay next access Accesses of a burst ROMFor Flash and SRAM, this determines the write pulse width Expansion Memory Pcmcia Configuration Register Mecr Bclk Cycle Time-ns BSxx Bit EncodingBclk Speeds for 160-MHz Processor Core Frequency Bclksel Dram Row/Column Address Multiplexing Dynamic Interface OperationDram Overview Dram Memory Size Options Dram Timing Mdcnfgtrp = 4 MDCNFGCDB2 = Addr Dram Burst-of-Eight Transactions 10-18 Dram Self-Refresh in Sleep ModeStatic Memory Interface Dram Refresh ROM Interface Overview ROM Timing Diagrams and Parameters 10-20 A255A42 Input Data Latch SA-1100 Developer’s Manual Eight Beat Burst Read from Burst-of-Four ROM Sram Timing Diagrams and Parameters Sram Write Timing Diagram 4-Beat BurstSram Interface Overview Flash Eprom Interface Overview 10-24 Flash Eprom Timing Diagrams and Parameters General Memory BUS Timing Static Access Followed by a Dram AccessDram Access Followed by a Static Access Dram Access Followed by a Refresh Operation 10-26 Pcmcia Overview Address 10.6.1 32-Bit Data Bus Operation 10-28 External Logic for Pcmcia Implementation 12. Pcmcia External Logic for a Two-Socket Configuration 10-30 13. Pcmcia External Logic for a One-Socket Configuration 14. Pcmcia Voltage-Control Logic Pcmcia Interface Timing Diagrams and Parameters 10-32 15. Pcmcia Memory or I/O 16-Bit Access 16. Pcmcia I/O 16-Bit Access to 8-Bit Device Flow of Events After Reset or Exiting Sleep Mode Initialization of the Memory Interface10-34 Alternate Memory Bus Master Mode Page Read/Write Interface Peripheral Control Module Peripheral Register Width DMA Burst Size Memory Organization ICP Hssp Peripheral Units’ Base AddressesPeripheral Serial Protocol Base Address LCD Controller 0h B010 Serial Port Peripheral InterruptsPeripheral Units’ Interrupt Numbers Interrupt Peripheral Pins Dedicated Peripheral PinsPeripheral Gpio Pin Function Peripheral Unit Gpio Pin Assignment Use of the Gpio Pins for Alternate Functions DMA Register Definitions DMA Controller DMA Device Address Register DDARn D31 D0 1 0 from memory Controller From Half-word wideDevice From To Half-word wide To From Byte-wide Valid Settings for the DDARn Register Ddar Fields Unit Name Function Address DA318 DS3011-10 DMA Control/Status Register DCSRn DMA Buffer a Transfer Count Register DBTAn DMA Buffer a Start Address Register DBSAn TCB120 Transfer count buffer B DMA OperationDMA Buffer B Start Address Register DBSBn DMA Buffer B Transfer Count Register DBTBn DMA Register List Physical Address Register Name Symbol DBTB3 DBSA3DBTA3 DBSB3 11-16 LCD Controller Lpclk 11-18 LCD Controller OperationDMA to Memory Interface Frame Buffer PBS Frame to palette 13..12Pixel bit size To palette Encoded Pixel Data70 Bit Unused Red Data30 Green Data30 Blue Data30Encoded Pixel Data150 11-22 FrameBufferSize = 32 + 16 + è Lookup Palette Input Fifo Dither Value Intensity Modulation Rate Color/Gray-Scale DitheringOutput Fifo Color/Gray-Scale Intensities and Modulation Rates LCD Controller Register Definitions LCD Controller Pins Single-/Dual-Panel Select SDS LCD Enable LENLCD Controller Control Register Color/Monochrome Select CMS Single Passive Screen Portion Pins LCD Controller Data Pin UtilizationDual Panel Active Panel 11-28 LCD Data-Pin Pixel Ordering Passive/Active Display Select PAS LCD Disable Done Interrupt Mask LDMBase Address Update Interrupt Mask BAM Error Interrupt Mask ERM 11-30 Double-Pixel Data DPD Pin Mode Palette DMA Request Delay PDD11.7.3.8 Big/Little Endian Select BLE LDM LENCMS SDS PDD PASBLE DPD 11-34 Pixels Per Line PPLHorizontal Sync Pulse Width HSW End-of-Line Pixel Clock Wait Count ELW ELW Beginning-of-Line Pixel Clock Wait Count BLWPPL HSW Lines Per Panel LPP Vertical Sync Pulse Width VSW11-36 Beginning-of-Frame Line Clock Wait Count BFW End-of-Frame Line Clock Wait Count EFW BFW LPPVSW EFW AC Bias Pin Frequency ACB Pixel Clock Divider PCD Pixel Clock Polarity PCP AC Bias Pin Transitions Per Interrupt APIVertical Sync Polarity VSP Horizontal Sync Polarity HSP Address 0h B010 Output Enable Polarity OEP OEP LCD Controller DMA RegistersHSP PCP DMA channel 1 base address pointer DMA Channel 1 Base Address Register31..0 DBAR1 Equal to the calculated end address of the buffer DMA Channel 1 Current Address RegisterDCAR1 DMA channel 1 current address pointer DMA channel 2 current address pointer DMA Channel 2 Base and Current Address RegistersDBAR2 DCAR2 LCD Controller Status Register LCD Disable Done Flag LDD read/write, maskable interruptBase Address Update Flag BAU read-only, maskable interrupt Bus Error Status BER read/write, maskable interrupt AC Bias Count Status ABC read/write, nonmaskable interrupt BAU LDD IUL BERABC IOL LCD Controller Control, DMA, and Status Register Locations LCD Controller Register Locations LDDx0 LCD Controller Pin Timing Diagrams Lfclk Llclk Lpclk LDDx011-52 DPD = 12. Passive Mode Pixel Clock and Data Pin Timing 11-54 13. Active Mode Timing 14. Active Mode Pixel Clock and Data Pin Timing Serial Port 0 USB Device Controller USB Operation11-56 Port Signalling Levels10. USB Bus States Bus State UDC+/UDC- Pin Levels Bit Encoding Bit Value Digital Data Nrzi Data11-58 Endpoint Field Formats11. Endpoint Field Addressing Endpoint Field Value UDC Endpoint Selected CRC16 Packet FormatsPID CRC5 Packets from UDC to host are boldface Transaction FormatsAction OUT 11-62 Setup DATA0UDC Device Requests Action Token Packet Data Packet UDC Register Definitions 12. Host Device Request SummaryRequest Name UDC Control Register Udccr Reset Interrupt Mask REMSuspend/Resume Interrupt Mask SRM Address 0h 8000 Udcomp UDC Address RegisterUDC OUT Max Packet Register Udcar UDC in Max Packet Register Address 0h 8000 000CUdcimp UDC Endpoint 0 Control/Status Register SSE Serviced Setup End SSEUDCCS0 SSE FST SST IPR OPR Receive Packet Complete RPC Receive Fifo Service RFSReceive Packet Error RPE UDC Endpoint 1 Control/Status Register RNE Bits 7..6 ReservedUDCCS1 RNE FST SST RPE RPC RFS Transmit Packet Complete TPC Transmit Fifo Service TFSTransmit Packet Error TPE UDC Endpoint 2 Control/Status Register FST SST TUR TPE TPC TFS UDCCS2 Data UDC Endpoint 0 Data RegisterUDC Endpoint 0 Write Count Register UDCD0 Read Bottom of receive Fifo data UDC Data RegisterUddr Top/bottom of transmit/receive Fifo data UDC Status/Interrupt Register Rstir Reset Interrupt Request RstirUdcsr Rstir Resir Susir TIR RIR EIR Serial Port 1 SDLC/UART UDC Register Locations13. UDC Control, Data, and Status Register Locations Sdlc Operation CRC-CCITT Frame FormatAddress Field Control Field Data Field CRC FieldBaud Rate Generation 11-82 Receive Operation Simultaneous Use of the Uart and Sdlc Transmit Operation 11-84 CPU and DMA Register Access SizesSdlc Register Definitions Transmit and Receive FIFOs Single/Double Flag Select SDF Loopback Mode LBMSdlc Control Register SDLC/UART Select SUS 11-86 Sample Clock Enable SCEBit Modulation Select BMS Sample Clock Direction SCD SDCR0 Receive Clock Edge Select RCETransmit Clock Edge Select TCE Address 0h 8002 TCE Abort After Frame AAF Transmit Fifo Interrupt Enable TIE Transmit Enable TXEReceive Enable RXE Receive Fifo Interrupt Enable RIE 11-90 Address Match Enable AMEReceiver Abort Interrupt EnableRAE Transmit Fifo Underrun Select TUS RAE SDCR1Read/Write RAE TUS AME TIE RIE RXE TXE AAF Address Match Value AMV SDCR2AMV SDCR3 Sdlc Control Registers 3Baud Rate Divisor BRD Address 0h 8002 006C 11-94 Sdlc Data Register ROR Address 0h 0078Sddr ROR CRE EOF 11-96 Sdlc Status RegisterTransmit Underrun Status TUR read/write, maskable interrupt Receiver Abort Status RAB read/write, maskable interrupt SA-1100 Developer’s Manual 11-97 RFS TFS RAB TUR EIF SDSR0 Transmit Fifo Not Full Flag TNF read-only, noninterruptible Receiver Synchronized Flag RSY read-only, noninterruptibleTransmitter Busy Flag TBY read-only, noninterruptible Receive Fifo Not Empty Flag RNE read-only, noninterruptible CRC Error Status CRE read-only, noninterruptible Receiver Overrun Status ROR read-only, noninterruptible11-100 TBY SDSR1ROR CRE EOF RTD TNF RNE RSY 14. Uart Control, Data, and Status Register Locations Uart Register Locations Serial Port 2 Infrared Communications Port ICP Sdlc Register Locations15. Sdlc Control, Data, and Status Register Locations 11-104 Low-Speed ICP OperationHP-SIR*Modulation Uart Frame Format High-Speed ICP Operation 11.10.2.1 4PPM ModulationChip Timeslots Data = Hssp Frame Format SA-1100 Developer’s Manual 11-107 11-108 SA-1100 Developer’s Manual 11-109 11-110 Uart Control Register HP-SIR Enable HSELow-Power Mode LPM Uart Register Definition LPM Hssp Register DefinitionsHssp Control Register IrDA Transmission Rate ITR SA-1100 Developer’s Manual 11-113 11-114 Address 0h 8004 HSCR0AME TIM RIM RXE TXE TUS LBM ITR HSCR1 Search for the next preamble11-116 Receive Pin Polarity Select RXP Transmit Pin Polarity Select TXP RXP 0h 9006HSCR2 RXP TXP Hssp Data Register HSSR1 Address 0h 8004 006CHsdr Last Fifo entry is transferred to the ROR bit Receiver Abort Status RAB read/write, nonmaskable interrupt Hssp Status Register 11-122 FRE Framing Error Status FRE read/write, nonmaskable interruptHSSR0 FRE RFS TFS RAB TUR EIF 11-124 End-of-Frame Flag EOF read-only, noninterruptible SA-1100 Developer’s Manual 11-125 ROR CRE EOF TNF RNE TBY RSY HSSR1 Hssp Register Locations 16. Uart Control, Data, and Status Register Locations17. Hssp Control, Data, and Status Register Locations 11-128 Serial Port 3 UartUart Operation LSB MSB 30. NRZ Bit Encoding Example 0100 11-130 Parity Enable PE Uart Register Definitions11.11.3.2 Odd/Even Parity Select OES Stop Bit Select SBS Data Size Select DSS11-132 TCE RCE SCE DSS SBS OES UTCR0 UTCR2 Bit Reset BRD70Uart Control Registers 1 UTCR1 Receiver Enable RXE Transmitter Enable TXEBreak BRK LBM TIE RIE BRK TXE RXE UTCR3 Uart Data Register ROR FRE PRE Utdr Uart Status Register Error in Fifo Flag EIF read-only, nonmaskable interrupt Receiver Idle Status RID read/write, maskable interrupt11-140 Address 0h 8005 001C UTSR0EIF REB RBB RID RFS TFS 11-142 Parity Error Flag PRE read-only, noninterruptible Receiver Overrun Flag ROR read-only, noninterruptible Framing Error Flag FRE read-only, noninterruptible UTSR1 Read-OnlyROR FRE PRE TNF RNE TBY Serial Port 4 MCP / SSP 11-146 MCP Operation 31. MCP Frame Data Format 11-148 Audio and Telecom Sample Rates and Data Transfer MCP Transmit and Receive Fifo Operation Codec Control Register Data Transfer Bit Audio Data Telecom Data11-150 Alternate SSP Pin Assignment External Clock Operation 11-152 MCP Register DefinitionsMCP Control Register Audio Sample Rate Divisor ASD Telecom Sample Rate Divisor TSD 11-154 Multimedia Communications Port Enable MCE11.12.3.5 A/D Sampling Mode ADM External Clock Select ECS Audio Receive Fifo Interrupt Enable are Telecom Transmit Fifo Interrupt Enable TTETelecom Receive Fifo Interrupt Enable TRE Audio Transmit Fifo Interrupt Enable ATE TSD External Clock Prescaler ECPASD Audio sample rate divisor TTE MCEECS ADM MCP Data Registers Clock Frequency Select CFSCFS 15..4 MCP Data RegisterAddress 0h 8006 MCP Data Register 0 MCDR0 Read/Write Reserved for future enhancements Address 0h 8006 000C MCP Data Register 1 MCDR1 Read/Write SA-1100 Developer’s Manual 11-161 Register read Read/write Read Returns a zero Reg Address R/W Reset BitAddress 0h 8006 MCP Data Register 2 MCDR2 Read/Write 15..0 Codec MCP Status Register 11-164 SA-1100 Developer’s Manual 11-165 Codec Read Completed Flag CRC read-only, noninterruptible Audio Codec Enabled Flag ACE read-only, noninterruptibleTelecom Codec Enabled Flag TCE read-only, noninterruptible Codec Write Completed Flag CWC read-only, noninterruptible TRS ATSARS TTS ANE TTUTRO ANF SSP Operation 11-170 35. Texas Instruments* Synchronous Serial Frame Format 36. Motorola* SPI Frame Format 11-172 37. National Microwire* Frame Format Bit Bit Data SSP Transmit and Receive FIFOs SSP Register Definitions SSP Control Register11-174 Frame Format FRF Synchronous Serial Port Enable SSE Serial Clock Rate SCR FRFSCR Serial Clock Polarity SPO 11-178 Serial Clock Phase SPHSclk SPO=0 Sclk SPO=1 Sfrm TXD4 RXD4 LSB SPO SSP Data Register Address 0h 8007 006CJustifies data and zero fills unused bits 11-180 SSP Busy Flag BSY read-only, noninterruptible SSP Status Register BSY 20. SSP Control, Data, and Status Register Locations MCP Register LocationsSSP Register Locations 19. MCP Control, Data, and Status Register Locations Peripheral Pin Controller PPC PPC Operation11-184 PPC Pin Direction Register PPC Register Definitions Sclk Address 0h 9006 Ppsr PPC Pin StateRegister Read/Write PPC Pin State Register Read Current state of LCD line clock pin returned LCD pixel clock pin stateRead Current state of LCD pixel clock pin returned LCD line clock pin state UPR PPC Pin Assignment RegisterUart Pin Reassignment UPR SSP Pin Reassignment SPR 11-190 PPC Sleep Mode Pin Direction Register LCD line clock pin configured as input during sleep LCD pixel clock sleep mode pin directionLCD pixel clock pin configured as input during sleep LCD line clock sleep mode pin direction PPC Pin Flag Register 21. PPC Control and Flag Register Locations PPC Register LocationsPage SA-1100 DC Maximum Ratings Symbol Parameter Min Max UnitsDC Parameters Absolute Maximum Ratings × Vddx Symbol Parameter Min Nom Max UnitsDC Operating Conditions SA-1100 DC Operating Conditions Vddx Power Supply Voltages and CurrentsParameter SA-1100 Units VDDPage AC Parameters Test ConditionsSA-1100 Output Derating 13-2 Memory Bus and Pcmcia Signal TimingsModule Considerations Memory Bus Memory Bus Out LCD Controller Signals MCP SignalsLLDD70 fall Sfrmc Pin Name Symbol Parameter Min Max UnitTiming Parameters SA-1100 AC Timing Table for AA and BA Parts Asynchronous Signal Timing Descriptions Page Mechanical Data and Packaging Information Package and Pinout 14-2 SA-1100 Pinout 208-Pin Quad Flat Pack SA-1100 256 Mini-Ball Grid Array Mechanical Drawing Mini-Ball Grid Array mBGA 14-4 SA-1100 Pinout 256-Pin Mini-Ball Grid Array Debug Support Instruction BreakpointData Breakpoint Page Boundary-Scan Test Interface Test Access Port TAP Controller State Transitions Public Instructions ResetPull-Up Resistors Instruction Register Extest SAMPLE/PRELOADClamp 16-4 HighzIdcode Bypass Bypass Register Test Data Registers 16.6.2 SA-1100 Device Identification ID Code Register 16.6.3 SA-1100 Boundary-Scan BS Register16-6 Tbsoh Tbsod Data Tbsss Tbssh Data Out Tbsdh Tbsdd Boundary-Scan Interface SignalsTbscl Tbsch Tbsis Tbsih Tbsrs Tbsrh TbsoeData Out Tbsde Tbsr SA-1100 Boundary-Scan Interface Timing Symbol Parameter Minimum Typical Maximum UnitsPage Register Summary Tucr B000 0054 B000 0044DMA control/status register 2 write ones to set B000 0048 Write ones to clear 004C Read only 0050 Ucdomp 8004 007C 0h 8004 Ffff Reserved Sdlc Registers Serial Port 80028031 8003 Reserved 8003 001C Uart Registers Serial Port 8005 8007 0078 0h 8007 Ffff Reserved PPC Registers 90069006 0034 0h 9006 Ffff Reserved MHz Oscillator Specifications B SpecificationsSystem Specifications Specification Minimum Typical Maximum Unit MHz Oscillator Specifications Quartz Crystal Specification SpecificationTypical Maximum Unit Page Startup Time KHz Oscillator Specifications CTemperature Range Current Consumption Parasitic Resistance Between Txtal or Textal and VSS Frequency Shift Due to Temperature Effect on the CircuitParasitic Capacitance Off-chip Between Txtal and Textal Parasitic Resistance Between Txtal and Textal Following table Other providers supply a Quality Factor, Q, instead of RmTherefore, the values for Q Corresponding to specified range of Rm are supplied KHz Oscillator Specifications Internal Test Test Unit Control Register TucrPMD TSEL2 TSEL1 TSEL0 TSEL2-0Page Support, Products, and Documentation

Peripheral Control Module

11.8.7.8Serviced Setup End (SSE)

Address: 0h 8000 0010

UDCCS0

SSE

FST

SST

IPR

OPR

Bit

SSE