Intel SA-1100 manual Peripheral Control Module

	10.5.3 DRAM Access Followed by a Refresh Operation		10-25
10.6	PCMCIA Overview		10-26
	10.6.1 32-Bit Data Bus Operation		10-27
	10.6.2 External Logic for PCMCIA Implementation		10-28
	10.6.3 PCMCIA Interface Timing Diagrams and Parameters		10-31
10.7 Initialization of the Memory Interface			10-34
	10.7.1 Flow of Events After Reset or Exiting Sleep Mode		10-34
10.8 Alternate Memory Bus Master Mode			10-35
11		Peripheral Control Module	11-1
11.1	Read/Write Interface		11-1
11.2	Memory Organization		11-2
11.3	Interrupts		11-4
11.4	Peripheral Pins		11-5
11.5 Use of the GPIO Pins for Alternate Functions			11-6
11.6	DMA Controller		11-7
	11.6.1	DMA Register Definitions	11-7
		11.6.1.1DMA Device Address Register (DDARn)	11-8
		11.6.1.2DMA Control/Status Register (DCSRn)	11-11
		11.6.1.3DMA Buffer A Start Address Register (DBSAn)	11-12
		11.6.1.4DMA Buffer A Transfer Count Register (DBTAn)	11-12
		11.6.1.5DMA Buffer B Start Address Register (DBSBn)	11-13
		11.6.1.6DMA Buffer B Transfer Count Register (DBTBn)	11-13
	11.6.2	DMA Operation	11-13
	11.6.3	DMA Register List	11-14
11.7	LCD Controller		11-16
	11.7.1	LCD Controller Operation	11-18
		11.7.1.1DMA to Memory Interface	11-18
		11.7.1.2Frame Buffer	11-18
		11.7.1.3Input FIFO	11-23
		11.7.1.4Lookup Palette	11-23
		11.7.1.5Color/Gray-Scale Dithering	11-24
		11.7.1.6Output FIFO	11-24
		11.7.1.7LCD Controller Pins	11-25
	11.7.2 LCD Controller Register Definitions		11-25
	11.7.3 LCD Controller Control Register 0		11-26
		11.7.3.1LCD Enable (LEN)	11-26
		11.7.3.2Color/Monochrome Select (CMS)	11-26
		11.7.3.3Single-/Dual-Panel Select (SDS)	11-26
		11.7.3.4LCD Disable Done Interrupt Mask (LDM)	11-29
		11.7.3.5Base Address Update Interrupt Mask (BAM)	11-29
		11.7.3.6Error Interrupt Mask (ERM)	11-29
		11.7.3.7Passive/Active Display Select (PAS)	11-29
		11.7.3.8Big/Little Endian Select (BLE)	11-31
		11.7.3.9Double-Pixel Data (DPD) Pin Mode	11-31
		11.7.3.10Palette DMA Request Delay (PDD)	11-31
	11.7.4 LCD Controller Control Register 1		11-34
		11.7.4.1Pixels Per Line (PPL)	11-34
		11.7.4.2Horizontal Sync Pulse Width (HSW)	11-34
		11.7.4.3End-of-Line Pixel Clock Wait Count (ELW)	11-34
		11.7.4.4Beginning-of-Line Pixel Clock Wait Count (BLW)	11-35
	11.7.5 LCD Controller Control Register 2		11-36

SA-1100 Developer’s Manual vii