SA-1100 Developer’s Manual 8-3
Clocks
8.3 Driving SA-1100 Crystal Pins from an External Source
In most applications, a 3.6864-MHz crystal will be connected between the PXTAL and the
PEXTAL pins. Similarly, a 32.768-kHz crystal will be connected between the TXTAL and
TEXTAL pins. In some applications, supplying these clocks from an external source may be
preferred. This is accommodated in the SA-1100 design by:
•Supplying the 32.768-kHz clock from an external source
— Only the TXTAL pin is driven. The TEXTAL pin must be left floating.
— The peak-to-peak voltage swing on TXTAL must be at least 0.6V and the voltage on the
pin must remain within the range of 0V to 1 V, independent of the other power supply
voltages applied to the processor.
•Supplying a 3.6864-MHz clock from an external source
— Both PXTAL and PEXTAL are driven with complementary signals.
— The peak-to-peak voltage swing on PXTAL and PEXTAL must be at least 0.6V and the
voltage on the pin must remain in the range of 0V to 1 V, independent of the other power
supply voltages applied to the processor.†
— When an external clock is being used, the pull-down path in the internal 3.6864MHz
oscillator is active. In order to limit the current into the internal oscillator, it is
recommended that the minimum impedance to the positive supply be controlled. The
maximum current sourced by the external clock source when the clock is at its maximum
positive voltage should be about 1 mA.†
— The maximum impedance of the external clock source is set by the minimum slew rate at
the PXTAL and PEXTAL pins, approximately 1 V per 100 ns.†
†These constraints can be satisfied by the following suggestions:
• For applications in which a pulse generator is available, drive differential 1-V signals through
series 1-K resistors (after the usual 50-ohm terminators-to-ground).
• To supply external clock signals from a 3.3-V supply, drive signals with open collector or
tristatable drivers. Set high level with 3.3K from 3.3 V to the output and 1.3K from the output
to ground.
• To supply external clock signals from a 1.5-V supply, drive signals with open collector or
tristatable drivers. Set high level with 1.5 K from 1.5V to the output and 2.7 K from output to
ground. This solution may be preferred in portable applications that turn off the 1.5-V supply
in sleep mode because this would eliminate the current through the resistors in sleep mode.
The two pairs of crystal pins are located close to each other on the processor. This arrangement is
advantageous when there are crystals connected to the pins because the low signal swings and slow
edges result in limited noise coupling between the pins. If one of the crystals is replaced by an
independent signal source and the other is not, some degradation of the remaining crystal oscillator
performance can result due to increased noise coupling. If only one crystal is being used, this effect
can be reduced by limiting the speed of the edge rate on the pin driven by the independent source.